arch/arm/include/debug/sa1100.S
Source file repositories/reference/linux-study-clean/arch/arm/include/debug/sa1100.S
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/include/debug/sa1100.S- Extension
.S- Size
- 1681 bytes
- Lines
- 68
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: arch/arm
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#define UTCR3 0x0c
#define UTDR 0x14
#define UTSR1 0x20
#define UTCR3_TXE 0x00000002 /* Transmit Enable */
#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
.macro addruart, rp, rv, tmp
mrc p15, 0, \rp, c1, c0
tst \rp, #1 @ MMU enabled?
moveq \rp, #0x80000000 @ physical base address
movne \rp, #0xf8000000 @ virtual address
@ We probe for the active serial port here, coherently with
@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
@ We assume r1 can be clobbered.
@ see if Ser3 is active
add \rp, \rp, #0x00050000
ldr \rv, [\rp, #UTCR3]
tst \rv, #UTCR3_TXE
@ if Ser3 is inactive, then try Ser1
addeq \rp, \rp, #(0x00010000 - 0x00050000)
ldreq \rv, [\rp, #UTCR3]
tsteq \rv, #UTCR3_TXE
@ if Ser1 is inactive, then try Ser2
addeq \rp, \rp, #(0x00030000 - 0x00010000)
ldreq \rv, [\rp, #UTCR3]
tsteq \rv, #UTCR3_TXE
@ clear top bits, and generate both phys and virt addresses
lsl \rp, \rp, #8
lsr \rp, \rp, #8
orr \rv, \rp, #0xf8000000 @ virtual
orr \rp, \rp, #0x80000000 @ physical
.endm
.macro senduart,rd,rx
str \rd, [\rx, #UTDR]
.endm
.macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UTSR1]
tst \rd, #UTSR1_TNF
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #UTSR1]
tst \rd, #UTSR1_TBY
bne 1001b
.endm
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.