arch/arm/kernel/cacheinfo.c
Source file repositories/reference/linux-study-clean/arch/arm/kernel/cacheinfo.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/kernel/cacheinfo.c- Extension
.c- Size
- 4252 bytes
- Lines
- 174
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/cacheinfo.hlinux/of.hasm/cachetype.hasm/cputype.hasm/system_info.h
Detected Declarations
function Copyrightfunction cache_line_sizefunction get_cache_typefunction ci_leaf_initfunction detect_cache_levelfunction early_cache_levelfunction init_cache_levelfunction populate_cache_leavesexport cache_line_size
Annotated Snippet
if (ctype == CACHE_TYPE_NOCACHE) {
level--;
break;
}
/* Separate instruction and data caches */
leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
}
*level_p = level;
*leaves_p = leaves;
return 0;
}
int early_cache_level(unsigned int cpu)
{
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
return detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves);
}
int init_cache_level(unsigned int cpu)
{
unsigned int level, leaves;
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
int fw_level;
int ret;
ret = detect_cache_level(&level, &leaves);
if (ret)
return ret;
fw_level = of_find_last_cache_level(cpu);
if (level < fw_level) {
/*
* some external caches not specified in CLIDR_EL1
* the information may be available in the device tree
* only unified external caches are considered here
*/
leaves += (fw_level - level);
level = fw_level;
}
this_cpu_ci->num_levels = level;
this_cpu_ci->num_leaves = leaves;
return 0;
}
int populate_cache_leaves(unsigned int cpu)
{
unsigned int level, idx;
enum cache_type type;
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
unsigned int arch = cpu_architecture();
/* CLIDR is not present before ARMv7/v7m */
if (arch < CPU_ARCH_ARMv7)
return -EOPNOTSUPP;
for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
idx < this_cpu_ci->num_leaves; idx++, level++) {
type = get_cache_type(level);
if (type == CACHE_TYPE_SEPARATE) {
ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
} else {
ci_leaf_init(this_leaf++, type, level);
}
}
return 0;
}
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/cacheinfo.h`, `linux/of.h`, `asm/cachetype.h`, `asm/cputype.h`, `asm/system_info.h`.
- Detected declarations: `function Copyright`, `function cache_line_size`, `function get_cache_type`, `function ci_leaf_init`, `function detect_cache_level`, `function early_cache_level`, `function init_cache_level`, `function populate_cache_leaves`, `export cache_line_size`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.