arch/arm/kernel/iwmmxt.S
Source file repositories/reference/linux-study-clean/arch/arm/kernel/iwmmxt.S
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/kernel/iwmmxt.S- Extension
.S- Size
- 7910 bytes
- Lines
- 357
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: arch/arm
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/linkage.hasm/ptrace.hasm/thread_info.hasm/asm-offsets.hasm/assembler.hiwmmxt.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <linux/linkage.h>
#include <asm/ptrace.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#include <asm/assembler.h>
#include "iwmmxt.h"
#define MMX_WR0 (0x00)
#define MMX_WR1 (0x08)
#define MMX_WR2 (0x10)
#define MMX_WR3 (0x18)
#define MMX_WR4 (0x20)
#define MMX_WR5 (0x28)
#define MMX_WR6 (0x30)
#define MMX_WR7 (0x38)
#define MMX_WR8 (0x40)
#define MMX_WR9 (0x48)
#define MMX_WR10 (0x50)
#define MMX_WR11 (0x58)
#define MMX_WR12 (0x60)
#define MMX_WR13 (0x68)
#define MMX_WR14 (0x70)
#define MMX_WR15 (0x78)
#define MMX_WCSSF (0x80)
#define MMX_WCASF (0x84)
#define MMX_WCGR0 (0x88)
#define MMX_WCGR1 (0x8C)
#define MMX_WCGR2 (0x90)
#define MMX_WCGR3 (0x94)
#define MMX_SIZE (0x98)
.text
.arm
ENTRY(iwmmxt_undef_handler)
push {r9, r10, lr}
get_thread_info r10
mov r9, pc
b iwmmxt_task_enable
mov r0, #0
pop {r9, r10, pc}
ENDPROC(iwmmxt_undef_handler)
/*
* Lazy switching of Concan coprocessor context
*
* r0 = struct pt_regs pointer
* r10 = struct thread_info pointer
* r9 = ret_from_exception
* lr = undefined instr exit
*
* called from prefetch exception handler with interrupts enabled
*/
ENTRY(iwmmxt_task_enable)
inc_preempt_count r10, r3
mrc p15, 0, r2, c15, c1, 0
@ CP0 and CP1 accessible?
tst r2, #0x3
bne 4f @ if so no business here
@ enable access to CP0 and CP1
orr r2, r2, #0x3
mcr p15, 0, r2, c15, c1, 0
ldr r3, =concan_owner
ldr r2, [r0, #S_PC] @ current task pc value
ldr r1, [r3] @ get current Concan owner
sub r2, r2, #4 @ adjust pc back
Annotation
- Immediate include surface: `linux/linkage.h`, `asm/ptrace.h`, `asm/thread_info.h`, `asm/asm-offsets.h`, `asm/assembler.h`, `iwmmxt.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.