arch/arm/mach-dove/pcie.c
Source file repositories/reference/linux-study-clean/arch/arm/mach-dove/pcie.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-dove/pcie.c- Extension
.c- Size
- 5407 bytes
- Lines
- 227
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/pci.hlinux/clk.hvideo/vga.hasm/mach/pci.hasm/mach/arch.hasm/setup.hasm/delay.hplat/pcie.hplat/addr-map.hirqs.hbridge-regs.hcommon.h
Detected Declarations
struct pcie_portfunction dove_pcie_setupfunction pcie_valid_configfunction pcie_rd_conffunction pcie_wr_conffunction rc_pci_fixupfunction pci_dev_for_each_resourcefunction dove_pcie_scan_busfunction dove_pcie_map_irqfunction add_pcie_portfunction dove_pcie_init
Annotated Snippet
struct pcie_port {
u8 index;
u8 root_bus_nr;
void __iomem *base;
spinlock_t conf_lock;
char mem_space_name[16];
struct resource res;
};
static struct pcie_port pcie_port[2];
static int num_pcie_ports;
static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
{
struct pcie_port *pp;
struct resource realio;
if (nr >= num_pcie_ports)
return 0;
pp = &pcie_port[nr];
sys->private_data = pp;
pp->root_bus_nr = sys->busnr;
/*
* Generic PCIe unit setup.
*/
orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
orion_pcie_setup(pp->base);
realio.start = sys->busnr * SZ_64K;
realio.end = realio.start + SZ_64K - 1;
pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
DOVE_PCIE1_IO_PHYS_BASE);
/*
* IORESOURCE_MEM
*/
snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
"PCIe %d MEM", pp->index);
pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
pp->res.name = pp->mem_space_name;
if (pp->index == 0) {
pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
} else {
pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
}
pp->res.flags = IORESOURCE_MEM;
if (request_resource(&iomem_resource, &pp->res))
panic("Request PCIe Memory resource failed\n");
pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
return 1;
}
static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
/*
* Don't go out when trying to access nonexisting devices
* on the local bus.
*/
if (bus == pp->root_bus_nr && dev > 1)
return 0;
return 1;
}
static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
struct pci_sys_data *sys = bus->sysdata;
struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
spin_lock_irqsave(&pp->conf_lock, flags);
ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
spin_unlock_irqrestore(&pp->conf_lock, flags);
return ret;
}
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/pci.h`, `linux/clk.h`, `video/vga.h`, `asm/mach/pci.h`, `asm/mach/arch.h`, `asm/setup.h`, `asm/delay.h`.
- Detected declarations: `struct pcie_port`, `function dove_pcie_setup`, `function pcie_valid_config`, `function pcie_rd_conf`, `function pcie_wr_conf`, `function rc_pci_fixup`, `function pci_dev_for_each_resource`, `function dove_pcie_scan_bus`, `function dove_pcie_map_irq`, `function add_pcie_port`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.