arch/arm/mach-imx/cpuidle-imx6sx.c
Source file repositories/reference/linux-study-clean/arch/arm/mach-imx/cpuidle-imx6sx.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-imx/cpuidle-imx6sx.c- Extension
.c- Size
- 2644 bytes
- Lines
- 119
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/cpuidle.hlinux/cpu_pm.hlinux/module.hasm/cacheflush.hasm/cpuidle.hasm/suspend.hcommon.hcpuidle.hhardware.h
Detected Declarations
function Copyrightfunction imx6sx_enter_waitfunction imx6sx_cpuidle_init
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*/
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/module.h>
#include <asm/cacheflush.h>
#include <asm/cpuidle.h>
#include <asm/suspend.h>
#include "common.h"
#include "cpuidle.h"
#include "hardware.h"
static int imx6sx_idle_finish(unsigned long val)
{
/*
* for Cortex-A7 which has an internal L2
* cache, need to flush it before powering
* down ARM platform, since flushing L1 cache
* here again has very small overhead, compared
* to adding conditional code for L2 cache type,
* just call flush_cache_all() is fine.
*/
flush_cache_all();
cpu_do_idle();
return 0;
}
static __cpuidle int imx6sx_enter_wait(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
imx6_set_lpm(WAIT_UNCLOCKED);
switch (index) {
case 1:
cpu_do_idle();
break;
case 2:
imx6_enable_rbc(true);
imx_gpc_set_arm_power_in_lpm(true);
imx_set_cpu_jump(0, v7_cpu_resume);
/* Need to notify there is a cpu pm operation. */
cpu_pm_enter();
cpu_cluster_pm_enter();
ct_cpuidle_enter();
cpu_suspend(0, imx6sx_idle_finish);
ct_cpuidle_exit();
cpu_cluster_pm_exit();
cpu_pm_exit();
imx_gpc_set_arm_power_in_lpm(false);
imx6_enable_rbc(false);
break;
default:
break;
}
imx6_set_lpm(WAIT_CLOCKED);
return index;
}
static struct cpuidle_driver imx6sx_cpuidle_driver = {
.name = "imx6sx_cpuidle",
.owner = THIS_MODULE,
.states = {
/* WFI */
ARM_CPUIDLE_WFI_STATE,
/* WAIT */
{
.exit_latency = 50,
.target_residency = 75,
.flags = CPUIDLE_FLAG_TIMER_STOP,
.enter = imx6sx_enter_wait,
.name = "WAIT",
.desc = "Clock off",
},
/* WAIT + ARM power off */
{
/*
* ARM gating 31us * 5 + RBC clear 65us
* and some margin for SW execution, here set it
* to 300us.
*/
.exit_latency = 300,
Annotation
- Immediate include surface: `linux/cpuidle.h`, `linux/cpu_pm.h`, `linux/module.h`, `asm/cacheflush.h`, `asm/cpuidle.h`, `asm/suspend.h`, `common.h`, `cpuidle.h`.
- Detected declarations: `function Copyright`, `function imx6sx_enter_wait`, `function imx6sx_cpuidle_init`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.