arch/arm/mach-imx/headsmp.S
Source file repositories/reference/linux-study-clean/arch/arm/mach-imx/headsmp.S
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-imx/headsmp.S- Extension
.S- Size
- 746 bytes
- Lines
- 38
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: arch/arm
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
linux/linkage.hlinux/init.hasm/assembler.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
.arch armv7-a
diag_reg_offset:
.word g_diag_reg - .
.macro set_diag_reg
adr r0, diag_reg_offset
ldr r1, [r0]
add r1, r1, r0 @ r1 = physical &g_diag_reg
ldr r0, [r1]
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
.endm
ENTRY(v7_secondary_startup)
ARM_BE8(setend be) @ go BE8 if entered LE
mrc p15, 0, r0, c0, c0, 0
lsl r0, r0, #16
lsr r0, r0, #20
/* 0xc07 is cortex A7's ID */
mov r1, #0xc00
orr r1, #0x7
cmp r0, r1
beq secondary_startup
set_diag_reg
b secondary_startup
ENDPROC(v7_secondary_startup)
Annotation
- Immediate include surface: `linux/linkage.h`, `linux/init.h`, `asm/assembler.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.