arch/arm/mach-imx/pm-imx5.c

Source file repositories/reference/linux-study-clean/arch/arm/mach-imx/pm-imx5.c

File Facts

System
Linux kernel
Corpus path
arch/arm/mach-imx/pm-imx5.c
Extension
.c
Size
11372 bytes
Lines
422
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct imx5_suspend_io_state {
	u32	offset;
	u32	clear;
	u32	set;
	u32	saved_value;
};

struct imx5_pm_data {
	phys_addr_t ccm_addr;
	phys_addr_t cortex_addr;
	phys_addr_t gpc_addr;
	phys_addr_t m4if_addr;
	phys_addr_t iomuxc_addr;
	void (*suspend_asm)(void __iomem *ocram_vbase);
	const u32 *suspend_asm_sz;
	const struct imx5_suspend_io_state *suspend_io_config;
	int suspend_io_count;
};

static const struct imx5_suspend_io_state imx53_suspend_io_config[] = {
#define MX53_DSE_HIGHZ_MASK (0x7 << 19)
	{.offset = 0x584, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM0 */
	{.offset = 0x594, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM1 */
	{.offset = 0x560, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM2 */
	{.offset = 0x554, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM3 */
	{.offset = 0x574, .clear = MX53_DSE_HIGHZ_MASK}, /* CAS */
	{.offset = 0x588, .clear = MX53_DSE_HIGHZ_MASK}, /* RAS */
	{.offset = 0x578, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_0 */
	{.offset = 0x570, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_1 */

	{.offset = 0x580, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT0 */
	{.offset = 0x564, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT1 */
	{.offset = 0x57c, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS0 */
	{.offset = 0x590, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS1 */
	{.offset = 0x568, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS2 */
	{.offset = 0x558, .clear = MX53_DSE_HIGHZ_MASK}, /* SDSQ3 */
	{.offset = 0x6f0, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_ADDS */
	{.offset = 0x718, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_BODS */
	{.offset = 0x71c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B1DS */
	{.offset = 0x728, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B2DS */
	{.offset = 0x72c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B3DS */

	/* Controls the CKE signal which is required to leave self refresh */
	{.offset = 0x720, .clear = MX53_DSE_HIGHZ_MASK, .set = 1 << 19}, /* CTLDS */
};

static const struct imx5_pm_data imx51_pm_data __initconst = {
	.ccm_addr = 0x73fd4000,
	.cortex_addr = 0x83fa0000,
	.gpc_addr = 0x73fd8000,
};

static const struct imx5_pm_data imx53_pm_data __initconst = {
	.ccm_addr = 0x53fd4000,
	.cortex_addr = 0x63fa0000,
	.gpc_addr = 0x53fd8000,
	.m4if_addr = 0x63fd8000,
	.iomuxc_addr = 0x53fa8000,
	.suspend_asm = &imx53_suspend,
	.suspend_asm_sz = &imx53_suspend_sz,
	.suspend_io_config = imx53_suspend_io_config,
	.suspend_io_count = ARRAY_SIZE(imx53_suspend_io_config),
};

#define MX5_MAX_SUSPEND_IOSTATE ARRAY_SIZE(imx53_suspend_io_config)

/*
 * This structure is for passing necessary data for low level ocram
 * suspend code(arch/arm/mach-imx/suspend-imx53.S), if this struct
 * definition is changed, the offset definition in that file
 * must be also changed accordingly otherwise, the suspend to ocram
 * function will be broken!
 */
struct imx5_cpu_suspend_info {
	void __iomem	*m4if_base;
	void __iomem	*iomuxc_base;
	u32		io_count;
	struct imx5_suspend_io_state io_state[MX5_MAX_SUSPEND_IOSTATE];
} __aligned(8);

static void __iomem *ccm_base;
static void __iomem *cortex_base;
static void __iomem *gpc_base;
static void __iomem *suspend_ocram_base;
static void (*imx5_suspend_in_ocram_fn)(void __iomem *ocram_vbase);

/*
 * set cpu low power mode before WFI instruction. This function is called
 * mx5 because it can be used for mx51, and mx53.
 */

Annotation

Implementation Notes