arch/arm/mach-imx/tzic.c

Source file repositories/reference/linux-study-clean/arch/arm/mach-imx/tzic.c

File Facts

System
Linux kernel
Corpus path
arch/arm/mach-imx/tzic.c
Extension
.c
Size
5883 bytes
Lines
221
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

while (stat) {
				handled = 1;
				irqofs = fls(stat) - 1;
				generic_handle_domain_irq(domain, irqofs + i * 32);
				stat &= ~(1 << irqofs);
			}
		}
	} while (handled);
}

/*
 * This function initializes the TZIC hardware and disables all the
 * interrupts. It registers the interrupt enable and disable functions
 * to the kernel for each interrupt source.
 */
static int __init tzic_init_dt(struct device_node *np, struct device_node *p)
{
	int irq_base;
	int i;

	tzic_base = of_iomap(np, 0);
	WARN_ON(!tzic_base);

	/* put the TZIC into the reset value with
	 * all interrupts disabled
	 */
	i = imx_readl(tzic_base + TZIC_INTCNTL);

	imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
	imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
	imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);

	for (i = 0; i < 4; i++)
		imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));

	/* disable all interrupts */
	for (i = 0; i < 4; i++)
		imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));

	/* all IRQ no FIQ Warning :: No selection */

	irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
	WARN_ON(irq_base < 0);

	domain = irq_domain_create_legacy(of_fwnode_handle(np), TZIC_NUM_IRQS, irq_base, 0,
					  &irq_domain_simple_ops, NULL);
	WARN_ON(!domain);

	for (i = 0; i < 4; i++, irq_base += 32)
		tzic_init_gc(i, irq_base);

	set_handle_irq(tzic_handle_irq);

#ifdef CONFIG_FIQ
	/* Initialize FIQ */
	init_FIQ(FIQ_START);
#endif

	pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");

	return 0;
}
IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt);

/**
 * tzic_enable_wake() - enable wakeup interrupt
 *
 * @return			0 if successful; non-zero otherwise
 *
 * This function provides an interrupt synchronization point that is required
 * by tzic enabled platforms before entering imx specific low power modes (ie,
 * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
 */
int tzic_enable_wake(void)
{
	unsigned int i;

	imx_writel(1, tzic_base + TZIC_DSMINT);
	if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
		return -EAGAIN;

	for (i = 0; i < 4; i++)
		imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
			   tzic_base + TZIC_WAKEUP0(i));

	return 0;
}

Annotation

Implementation Notes