arch/arm/mach-lpc32xx/common.c
Source file repositories/reference/linux-study-clean/arch/arm/mach-lpc32xx/common.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-lpc32xx/common.c- Extension
.c- Size
- 3019 bytes
- Lines
- 126
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/soc/nxp/lpc32xx-misc.hasm/mach/map.hasm/system_info.hlpc32xx.hcommon.h
Detected Declarations
function Copyrightfunction lpc32xx_return_iramfunction lpc32xx_set_phy_interface_modefunction lpc32xx_map_iofunction lpc32xx_check_uidexport lpc32xx_return_iramexport lpc32xx_set_phy_interface_mode
Annotated Snippet
if (savedval1 == savedval2) {
__raw_writel(savedval2 + 1, iramptr2);
if (__raw_readl(iramptr1) == savedval2 + 1)
iram_size = LPC32XX_IRAM_BANK_SIZE;
else
iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
__raw_writel(savedval2, iramptr2);
} else
iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
}
if (dmaaddr)
*dmaaddr = LPC32XX_IRAM_BASE;
if (mapbase)
*mapbase = io_p2v(LPC32XX_IRAM_BASE);
return iram_size;
}
EXPORT_SYMBOL_GPL(lpc32xx_return_iram);
void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
{
u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
if (mode == PHY_INTERFACE_MODE_MII)
tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
else
tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
__raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
}
EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode);
static struct map_desc lpc32xx_io_desc[] __initdata = {
{
.virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
.pfn = __phys_to_pfn(LPC32XX_AHB0_START),
.length = LPC32XX_AHB0_SIZE,
.type = MT_DEVICE
},
{
.virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
.pfn = __phys_to_pfn(LPC32XX_AHB1_START),
.length = LPC32XX_AHB1_SIZE,
.type = MT_DEVICE
},
{
.virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
.pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
.length = LPC32XX_FABAPB_SIZE,
.type = MT_DEVICE
},
{
.virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
.pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
.length = (LPC32XX_IRAM_BANK_SIZE * 2),
.type = MT_DEVICE
},
};
void __init lpc32xx_map_io(void)
{
iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
}
static int __init lpc32xx_check_uid(void)
{
u32 uid[4];
lpc32xx_get_uid(uid);
printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
uid[3], uid[2], uid[1], uid[0]);
if (!system_serial_low && !system_serial_high) {
system_serial_low = uid[0];
system_serial_high = uid[1];
}
return 1;
}
arch_initcall(lpc32xx_check_uid);
Annotation
- Immediate include surface: `linux/init.h`, `linux/soc/nxp/lpc32xx-misc.h`, `asm/mach/map.h`, `asm/system_info.h`, `lpc32xx.h`, `common.h`.
- Detected declarations: `function Copyright`, `function lpc32xx_return_iram`, `function lpc32xx_set_phy_interface_mode`, `function lpc32xx_map_io`, `function lpc32xx_check_uid`, `export lpc32xx_return_iram`, `export lpc32xx_set_phy_interface_mode`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.