arch/arm/mach-mvebu/cpu-reset.c
Source file repositories/reference/linux-study-clean/arch/arm/mach-mvebu/cpu-reset.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-mvebu/cpu-reset.c- Extension
.c- Size
- 2031 bytes
- Lines
- 102
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/init.hlinux/of_address.hlinux/io.hlinux/resource.hcommon.h
Detected Declarations
function mvebu_cpu_reset_deassertfunction mvebu_cpu_reset_mapfunction mvebu_cpu_reset_init
Annotated Snippet
if (np) {
pr_warn(FW_WARN "deprecated pmsu binding\n");
res_idx = 1;
}
}
/* No reset node found */
if (!np)
return -ENODEV;
ret = mvebu_cpu_reset_map(np, res_idx);
of_node_put(np);
return ret;
}
early_initcall(mvebu_cpu_reset_init);
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/init.h`, `linux/of_address.h`, `linux/io.h`, `linux/resource.h`, `common.h`.
- Detected declarations: `function mvebu_cpu_reset_deassert`, `function mvebu_cpu_reset_map`, `function mvebu_cpu_reset_init`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.