arch/arm/mach-mvebu/mvebu-soc-id.c
Source file repositories/reference/linux-study-clean/arch/arm/mach-mvebu/mvebu-soc-id.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-mvebu/mvebu-soc-id.c- Extension
.c- Size
- 4070 bytes
- Lines
- 176
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/init.hlinux/io.hlinux/kernel.hlinux/of.hlinux/of_address.hlinux/slab.hlinux/sys_soc.hcommon.hmvebu-soc-id.h
Detected Declarations
function mvebu_get_soc_idfunction get_soc_id_by_pcifunction mvebu_soc_id_initfunction mvebu_soc_device
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* ID and revision information for mvebu SoCs
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* All the mvebu SoCs have information related to their variant and
* revision that can be read from the PCI control register. This is
* done before the PCI initialization to avoid any conflict. Once the
* ID and revision are retrieved, the mapping is freed.
*/
#define pr_fmt(fmt) "mvebu-soc-id: " fmt
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include "common.h"
#include "mvebu-soc-id.h"
#define PCIE_DEV_ID_OFF 0x0
#define PCIE_DEV_REV_OFF 0x8
#define SOC_ID_MASK 0xFFFF0000
#define SOC_REV_MASK 0xFF
static u32 soc_dev_id;
static u32 soc_rev;
static bool is_id_valid;
static const struct of_device_id mvebu_pcie_of_match_table[] = {
{ .compatible = "marvell,armada-xp-pcie", },
{ .compatible = "marvell,armada-370-pcie", },
{ .compatible = "marvell,kirkwood-pcie" },
{},
};
int mvebu_get_soc_id(u32 *dev, u32 *rev)
{
if (is_id_valid) {
*dev = soc_dev_id;
*rev = soc_rev;
return 0;
} else
return -ENODEV;
}
static int __init get_soc_id_by_pci(void)
{
struct device_node *np;
int ret = 0;
void __iomem *pci_base;
struct clk *clk;
struct device_node *child;
np = of_find_matching_node(NULL, mvebu_pcie_of_match_table);
if (!np)
return ret;
/*
* ID and revision are available from any port, so we
* just pick the first one
*/
child = of_get_next_child(np, NULL);
if (child == NULL) {
pr_err("cannot get pci node\n");
ret = -ENOMEM;
goto clk_err;
}
clk = of_clk_get_by_name(child, NULL);
if (IS_ERR(clk)) {
pr_err("cannot get clock\n");
ret = -ENOMEM;
goto clk_err;
}
ret = clk_prepare_enable(clk);
if (ret) {
pr_err("cannot enable clock\n");
goto clk_err;
}
Annotation
- Immediate include surface: `linux/clk.h`, `linux/init.h`, `linux/io.h`, `linux/kernel.h`, `linux/of.h`, `linux/of_address.h`, `linux/slab.h`, `linux/sys_soc.h`.
- Detected declarations: `function mvebu_get_soc_id`, `function get_soc_id_by_pci`, `function mvebu_soc_id_init`, `function mvebu_soc_device`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.