arch/arm/mach-mvebu/platsmp.c
Source file repositories/reference/linux-study-clean/arch/arm/mach-mvebu/platsmp.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-mvebu/platsmp.c- Extension
.c- Size
- 6468 bytes
- Lines
- 256
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/smp.hlinux/clk.hlinux/of.hlinux/of_address.hlinux/mbus.hasm/cacheflush.hasm/smp_plat.hcommon.harmada-370-xp.hpmsu.hcoherency.h
Detected Declarations
function armada_xp_boot_secondaryfunction armada_xp_secondary_initfunction armada_xp_smp_init_cpusfunction armada_xp_sync_secondary_clkfunction armada_xp_smp_prepare_cpusfunction armada_xp_cpu_diefunction armada_xp_cpu_killfunction mv98dx3236_resume_set_cpu_boot_addrfunction mv98dx3236_boot_secondary
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Symmetric Multi Processing (SMP) support for Armada XP
*
* Copyright (C) 2012 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Yehuda Yitschak <yehuday@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
* This file implements the routines for preparing the SMP infrastructure
* and waking up the secondary CPUs
*/
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/mbus.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include "common.h"
#include "armada-370-xp.h"
#include "pmsu.h"
#include "coherency.h"
#define ARMADA_XP_MAX_CPUS 4
#define AXP_BOOTROM_BASE 0xfff00000
#define AXP_BOOTROM_SIZE 0x100000
static struct clk *boot_cpu_clk;
static struct clk *get_cpu_clk(int cpu)
{
struct clk *cpu_clk;
struct device_node *np = of_get_cpu_node(cpu, NULL);
if (WARN(!np, "missing cpu node\n"))
return NULL;
cpu_clk = of_clk_get(np, 0);
if (WARN_ON(IS_ERR(cpu_clk)))
return NULL;
return cpu_clk;
}
static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int ret, hw_cpu;
pr_info("Booting CPU %d\n", cpu);
hw_cpu = cpu_logical_map(cpu);
mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
/*
* This is needed to wake up CPUs in the offline state after
* using CPU hotplug.
*/
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
/*
* This is needed to take secondary CPUs out of reset on the
* initial boot.
*/
ret = mvebu_cpu_reset_deassert(hw_cpu);
if (ret) {
pr_warn("unable to boot CPU: %d\n", ret);
return ret;
}
return 0;
}
/*
* When a CPU is brought back online, either through CPU hotplug, or
* because of the boot of a kexec'ed kernel, the PMSU configuration
* for this CPU might be in the deep idle state, preventing this CPU
* from receiving interrupts. Here, we therefore take out the current
* CPU from this state, which was entered by armada_xp_cpu_die()
* below.
*/
static void armada_xp_secondary_init(unsigned int cpu)
{
mvebu_v7_pmsu_idle_exit();
}
Annotation
- Immediate include surface: `linux/init.h`, `linux/smp.h`, `linux/clk.h`, `linux/of.h`, `linux/of_address.h`, `linux/mbus.h`, `asm/cacheflush.h`, `asm/smp_plat.h`.
- Detected declarations: `function armada_xp_boot_secondary`, `function armada_xp_secondary_init`, `function armada_xp_smp_init_cpus`, `function armada_xp_sync_secondary_clk`, `function armada_xp_smp_prepare_cpus`, `function armada_xp_cpu_die`, `function armada_xp_cpu_kill`, `function mv98dx3236_resume_set_cpu_boot_addr`, `function mv98dx3236_boot_secondary`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.