arch/arm/mach-omap1/irqs.h

Source file repositories/reference/linux-study-clean/arch/arm/mach-omap1/irqs.h

File Facts

System
Linux kernel
Corpus path
arch/arm/mach-omap1/irqs.h
Extension
.h
Size
8807 bytes
Lines
241
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
#define __ASM_ARCH_OMAP15XX_IRQS_H

/*
 * IRQ numbers for interrupt handler 1
 *
 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
 *
 */
#define INT_CAMERA		(NR_IRQS_LEGACY + 1)
#define INT_FIQ			(NR_IRQS_LEGACY + 3)
#define INT_RTDX		(NR_IRQS_LEGACY + 6)
#define INT_DSP_MMU_ABORT	(NR_IRQS_LEGACY + 7)
#define INT_HOST		(NR_IRQS_LEGACY + 8)
#define INT_ABORT		(NR_IRQS_LEGACY + 9)
#define INT_BRIDGE_PRIV		(NR_IRQS_LEGACY + 13)
#define INT_GPIO_BANK1		(NR_IRQS_LEGACY + 14)
#define INT_UART3		(NR_IRQS_LEGACY + 15)
#define INT_TIMER3		(NR_IRQS_LEGACY + 16)
#define INT_DMA_CH0_6		(NR_IRQS_LEGACY + 19)
#define INT_DMA_CH1_7		(NR_IRQS_LEGACY + 20)
#define INT_DMA_CH2_8		(NR_IRQS_LEGACY + 21)
#define INT_DMA_CH3		(NR_IRQS_LEGACY + 22)
#define INT_DMA_CH4		(NR_IRQS_LEGACY + 23)
#define INT_DMA_CH5		(NR_IRQS_LEGACY + 24)
#define INT_TIMER1		(NR_IRQS_LEGACY + 26)
#define INT_WD_TIMER		(NR_IRQS_LEGACY + 27)
#define INT_BRIDGE_PUB		(NR_IRQS_LEGACY + 28)
#define INT_TIMER2		(NR_IRQS_LEGACY + 30)
#define INT_LCD_CTRL		(NR_IRQS_LEGACY + 31)

/*
 * OMAP-1510 specific IRQ numbers for interrupt handler 1
 */
#define INT_1510_IH2_IRQ	(NR_IRQS_LEGACY + 0)
#define INT_1510_RES2		(NR_IRQS_LEGACY + 2)
#define INT_1510_SPI_TX		(NR_IRQS_LEGACY + 4)
#define INT_1510_SPI_RX		(NR_IRQS_LEGACY + 5)
#define INT_1510_DSP_MAILBOX1	(NR_IRQS_LEGACY + 10)
#define INT_1510_DSP_MAILBOX2	(NR_IRQS_LEGACY + 11)
#define INT_1510_RES12		(NR_IRQS_LEGACY + 12)
#define INT_1510_LB_MMU		(NR_IRQS_LEGACY + 17)
#define INT_1510_RES18		(NR_IRQS_LEGACY + 18)
#define INT_1510_LOCAL_BUS	(NR_IRQS_LEGACY + 29)

/*
 * OMAP-1610 specific IRQ numbers for interrupt handler 1
 */
#define INT_1610_IH2_IRQ	INT_1510_IH2_IRQ
#define INT_1610_IH2_FIQ	(NR_IRQS_LEGACY + 2)
#define INT_1610_McBSP2_TX	(NR_IRQS_LEGACY + 4)
#define INT_1610_McBSP2_RX	(NR_IRQS_LEGACY + 5)
#define INT_1610_DSP_MAILBOX1	(NR_IRQS_LEGACY + 10)
#define INT_1610_DSP_MAILBOX2	(NR_IRQS_LEGACY + 11)
#define INT_1610_LCD_LINE	(NR_IRQS_LEGACY + 12)
#define INT_1610_GPTIMER1	(NR_IRQS_LEGACY + 17)
#define INT_1610_GPTIMER2	(NR_IRQS_LEGACY + 18)
#define INT_1610_SSR_FIFO_0	(NR_IRQS_LEGACY + 29)

/*
 * OMAP-7xx specific IRQ numbers for interrupt handler 1
 */
#define INT_7XX_IH2_FIQ		(NR_IRQS_LEGACY + 0)
#define INT_7XX_IH2_IRQ		(NR_IRQS_LEGACY + 1)
#define INT_7XX_USB_NON_ISO	(NR_IRQS_LEGACY + 2)
#define INT_7XX_USB_ISO		(NR_IRQS_LEGACY + 3)
#define INT_7XX_ICR		(NR_IRQS_LEGACY + 4)
#define INT_7XX_EAC		(NR_IRQS_LEGACY + 5)
#define INT_7XX_GPIO_BANK1	(NR_IRQS_LEGACY + 6)
#define INT_7XX_GPIO_BANK2	(NR_IRQS_LEGACY + 7)
#define INT_7XX_GPIO_BANK3	(NR_IRQS_LEGACY + 8)
#define INT_7XX_McBSP2TX	(NR_IRQS_LEGACY + 10)
#define INT_7XX_McBSP2RX	(NR_IRQS_LEGACY + 11)
#define INT_7XX_McBSP2RX_OVF	(NR_IRQS_LEGACY + 12)
#define INT_7XX_LCD_LINE	(NR_IRQS_LEGACY + 14)
#define INT_7XX_GSM_PROTECT	(NR_IRQS_LEGACY + 15)
#define INT_7XX_TIMER3		(NR_IRQS_LEGACY + 16)
#define INT_7XX_GPIO_BANK5	(NR_IRQS_LEGACY + 17)
#define INT_7XX_GPIO_BANK6	(NR_IRQS_LEGACY + 18)
#define INT_7XX_SPGIO_WR	(NR_IRQS_LEGACY + 29)

/*
 * IRQ numbers for interrupt handler 2
 *
 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
 */
#define IH2_BASE		(NR_IRQS_LEGACY + 32)

#define INT_KEYBOARD		(1 + IH2_BASE)
#define INT_uWireTX		(2 + IH2_BASE)

Annotation

Implementation Notes