arch/arm/mach-omap1/mux.c
Source file repositories/reference/linux-study-clean/arch/arm/mach-omap1/mux.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-omap1/mux.c- Extension
.c- Size
- 18973 bytes
- Lines
- 460
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/init.hlinux/io.hlinux/spinlock.hlinux/soc/ti/omap1-io.hhardware.hmux.h
Detected Declarations
function omap1_cfg_regfunction omap_mux_registerfunction omap_cfg_regfunction omap1_mux_initexport omap_cfg_reg
Annotated Snippet
if (cfg->pu_pd_reg && cfg->pull_val) {
spin_lock_irqsave(&mux_spin_lock, flags);
pu_pd_orig = omap_readl(cfg->pu_pd_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pu_pd_val) {
if (!(pu_pd_orig & mask))
warn = 1;
/* Use pull up */
pu_pd = pu_pd_orig | mask;
} else {
if (pu_pd_orig & mask)
warn = 1;
/* Use pull down */
pu_pd = pu_pd_orig & ~mask;
}
omap_writel(pu_pd, cfg->pu_pd_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
}
/* Check for an associated pull down register */
if (cfg->pull_reg) {
spin_lock_irqsave(&mux_spin_lock, flags);
pull_orig = omap_readl(cfg->pull_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pull_val) {
if (pull_orig & mask)
warn = 1;
/* Low bit = pull enabled */
pull = pull_orig & ~mask;
} else {
if (!(pull_orig & mask))
warn = 1;
/* High bit = pull disabled */
pull = pull_orig | mask;
}
omap_writel(pull, cfg->pull_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
if (warn) {
#ifdef CONFIG_OMAP_MUX_WARNINGS
printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
}
#ifdef CONFIG_OMAP_MUX_DEBUG
if (cfg->debug || warn) {
printk("MUX: Setting register %s\n", cfg->name);
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
if (!cpu_is_omap15xx()) {
if (cfg->pu_pd_reg && cfg->pull_val) {
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pu_pd_name, cfg->pu_pd_reg,
pu_pd_orig, pu_pd);
}
}
if (cfg->pull_reg)
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pull_name, cfg->pull_reg, pull_orig, pull);
}
#endif
#ifdef CONFIG_OMAP_MUX_WARNINGS
return warn ? -ETXTBSY : 0;
#else
return 0;
#endif
}
static struct omap_mux_cfg *mux_cfg;
int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
{
if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
|| !arch_mux_cfg->cfg_reg) {
printk(KERN_ERR "Invalid pin table\n");
return -EINVAL;
}
mux_cfg = arch_mux_cfg;
return 0;
}
Annotation
- Immediate include surface: `linux/module.h`, `linux/init.h`, `linux/io.h`, `linux/spinlock.h`, `linux/soc/ti/omap1-io.h`, `hardware.h`, `mux.h`.
- Detected declarations: `function omap1_cfg_reg`, `function omap_mux_register`, `function omap_cfg_reg`, `function omap1_mux_init`, `export omap_cfg_reg`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.