arch/arm/mach-omap2/omap-headsmp.S

Source file repositories/reference/linux-study-clean/arch/arm/mach-omap2/omap-headsmp.S

File Facts

System
Linux kernel
Corpus path
arch/arm/mach-omap2/omap-headsmp.S
Extension
.S
Size
3545 bytes
Lines
134
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: arch/arm
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>

#include "omap44xx.h"

/* Physical address needed since MMU not enabled yet on secondary core */
#define AUX_CORE_BOOT0_PA			0x48281800
#define API_HYP_ENTRY				0x102

ENTRY(omap_secondary_startup)
#ifdef CONFIG_SMP
	b	secondary_startup
#else
/* Should never get here */
again:	wfi
	b	again
#endif
#ENDPROC(omap_secondary_startup)

/*
 * OMAP5 specific entry point for secondary CPU to jump from ROM
 * code.  This routine also provides a holding flag into which
 * secondary core is held until we're ready for it to initialise.
 * The primary core will update this flag using a hardware
 * register AuxCoreBoot0.
 */
ENTRY(omap5_secondary_startup)
wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
	ldr	r0, [r2]
	mov	r0, r0, lsr #5
	mrc	p15, 0, r4, c0, c0, 5
	and	r4, r4, #0x0f
	cmp	r0, r4
	bne	wait
	b	omap_secondary_startup
ENDPROC(omap5_secondary_startup)
/*
 * Same as omap5_secondary_startup except we call into the ROM to
 * enable HYP mode first.  This is called instead of
 * omap5_secondary_startup if the primary CPU was put into HYP mode by
 * the boot loader.
 */
	.arch armv7-a
	.arch_extension sec
ENTRY(omap5_secondary_hyp_startup)
wait_2:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
	ldr	r0, [r2]
	mov	r0, r0, lsr #5
	mrc	p15, 0, r4, c0, c0, 5
	and	r4, r4, #0x0f
	cmp	r0, r4
	bne	wait_2
	ldr	r12, =API_HYP_ENTRY
	badr	r0, hyp_boot
	smc	#0
hyp_boot:
	b	omap_secondary_startup
ENDPROC(omap5_secondary_hyp_startup)
/*
 * OMAP4 specific entry point for secondary CPU to jump from ROM
 * code.  This routine also provides a holding flag into which
 * secondary core is held until we're ready for it to initialise.
 * The primary core will update this flag using a hardware
 * register AuxCoreBoot0.
 */
ENTRY(omap4_secondary_startup)
hold:	ldr	r12,=0x103
	dsb
	smc	#0			@ read from AuxCoreBoot0

Annotation

Implementation Notes