arch/arm/mach-omap2/omap-iommu.c
Source file repositories/reference/linux-study-clean/arch/arm/mach-omap2/omap-iommu.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-omap2/omap-iommu.c- Extension
.c- Size
- 2981 bytes
- Lines
- 143
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/platform_device.hlinux/err.hlinux/clk.hlinux/list.hclockdomain.hpowerdomain.hcommon.h
Detected Declarations
struct pwrdm_linkfunction omap_iommu_dra7_emu_swsup_configfunction list_for_each_entryfunction omap_iommu_set_pwrdm_constraint
Annotated Snippet
struct pwrdm_link {
struct device *dev;
struct powerdomain *pwrdm;
struct list_head node;
};
static DEFINE_SPINLOCK(iommu_lock);
static struct clockdomain *emu_clkdm;
static atomic_t emu_count;
static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev,
bool enable)
{
struct device_node *np = pdev->dev.of_node;
unsigned long flags;
if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
return;
if (!emu_clkdm) {
emu_clkdm = clkdm_lookup("emu_clkdm");
if (WARN_ON_ONCE(!emu_clkdm))
return;
}
spin_lock_irqsave(&iommu_lock, flags);
if (enable && (atomic_inc_return(&emu_count) == 1))
clkdm_deny_idle(emu_clkdm);
else if (!enable && (atomic_dec_return(&emu_count) == 0))
clkdm_allow_idle(emu_clkdm);
spin_unlock_irqrestore(&iommu_lock, flags);
}
static struct powerdomain *_get_pwrdm(struct device *dev)
{
struct clk *clk;
struct clk_hw_omap *hwclk;
struct clockdomain *clkdm;
struct powerdomain *pwrdm = NULL;
struct pwrdm_link *entry;
unsigned long flags;
static LIST_HEAD(cache);
spin_lock_irqsave(&iommu_lock, flags);
list_for_each_entry(entry, &cache, node) {
if (entry->dev == dev) {
pwrdm = entry->pwrdm;
break;
}
}
spin_unlock_irqrestore(&iommu_lock, flags);
if (pwrdm)
return pwrdm;
clk = of_clk_get(dev->of_node->parent, 0);
if (IS_ERR(clk)) {
dev_err(dev, "no fck found\n");
return NULL;
}
hwclk = to_clk_hw_omap(__clk_get_hw(clk));
clk_put(clk);
if (!hwclk || !hwclk->clkdm_name) {
dev_err(dev, "no hwclk data\n");
return NULL;
}
clkdm = clkdm_lookup(hwclk->clkdm_name);
if (!clkdm) {
dev_err(dev, "clkdm not found: %s\n", hwclk->clkdm_name);
return NULL;
}
pwrdm = clkdm_get_pwrdm(clkdm);
if (!pwrdm) {
dev_err(dev, "pwrdm not found: %s\n", clkdm->name);
return NULL;
}
entry = kmalloc_obj(*entry);
if (entry) {
entry->dev = dev;
entry->pwrdm = pwrdm;
spin_lock_irqsave(&iommu_lock, flags);
list_add(&entry->node, &cache);
Annotation
- Immediate include surface: `linux/platform_device.h`, `linux/err.h`, `linux/clk.h`, `linux/list.h`, `clockdomain.h`, `powerdomain.h`, `common.h`.
- Detected declarations: `struct pwrdm_link`, `function omap_iommu_dra7_emu_swsup_config`, `function list_for_each_entry`, `function omap_iommu_set_pwrdm_constraint`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.