arch/arm/mach-omap2/omap-smp.c

Source file repositories/reference/linux-study-clean/arch/arm/mach-omap2/omap-smp.c

File Facts

System
Linux kernel
Corpus path
arch/arm/mach-omap2/omap-smp.c
Extension
.c
Size
11947 bytes
Lines
418
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct omap_smp_config {
	unsigned long cpu1_rstctrl_pa;
	void __iomem *cpu1_rstctrl_va;
	void __iomem *scu_base;
	void __iomem *wakeupgen_base;
	void *startup_addr;
};

static struct omap_smp_config cfg;

static const struct omap_smp_config omap443x_cfg __initconst = {
	.cpu1_rstctrl_pa = 0x4824380c,
	.startup_addr = omap4_secondary_startup,
};

static const struct omap_smp_config omap446x_cfg __initconst = {
	.cpu1_rstctrl_pa = 0x4824380c,
	.startup_addr = omap4460_secondary_startup,
};

static const struct omap_smp_config omap5_cfg __initconst = {
	.cpu1_rstctrl_pa = 0x48243810,
	.startup_addr = omap5_secondary_startup,
};

void __iomem *omap4_get_scu_base(void)
{
	return cfg.scu_base;
}

#ifdef CONFIG_OMAP5_ERRATA_801819
static void omap5_erratum_workaround_801819(void)
{
	u32 acr, revidr;
	u32 acr_mask;

	/* REVIDR[3] indicates erratum fix available on silicon */
	asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr));
	if (revidr & (0x1 << 3))
		return;

	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	/*
	 * BIT(27) - Disables streaming. All write-allocate lines allocate in
	 * the L1 or L2 cache.
	 * BIT(25) - Disables streaming. All write-allocate lines allocate in
	 * the L1 cache.
	 */
	acr_mask = (0x3 << 25) | (0x3 << 27);
	/* do we already have it done.. if yes, skip expensive smc */
	if ((acr & acr_mask) == acr_mask)
		return;

	acr |= acr_mask;
	omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);

	pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",
		 __func__, smp_processor_id());
}
#else
static inline void omap5_erratum_workaround_801819(void) { }
#endif

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
/*
 * Configure ACR and enable ACTLR[0] (Enable invalidates of BTB with
 * ICIALLU) to activate the workaround for secondary Core.
 * NOTE: it is assumed that the primary core's configuration is done
 * by the boot loader (kernel will detect a misconfiguration and complain
 * if this is not done).
 *
 * In General Purpose(GP) devices, ACR bit settings can only be done
 * by ROM code in "secure world" using the smc call and there is no
 * option to update the "firmware" on such devices. This also works for
 * High security(HS) devices, as a backup option in case the
 * "update" is not done in the "security firmware".
 */
static void omap5_secondary_harden_predictor(void)
{
	u32 acr, acr_mask;

	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));

	/*
	 * ACTLR[0] (Enable invalidates of BTB with ICIALLU)
	 */
	acr_mask = BIT(0);

	/* Do we already have it done.. if yes, skip expensive smc */
	if ((acr & acr_mask) == acr_mask)

Annotation

Implementation Notes