arch/arm/mach-omap2/opp2xxx.h
Source file repositories/reference/linux-study-clean/arch/arm/mach-omap2/opp2xxx.h
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-omap2/opp2xxx.h- Extension
.h- Size
- 15630 bytes
- Lines
- 431
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct prcm_config
Annotated Snippet
struct prcm_config {
unsigned long xtal_speed; /* crystal rate */
unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
unsigned long mpu_speed; /* speed of MPU */
unsigned long cm_clksel_mpu; /* mpu divider */
unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
unsigned long cm_clksel_gfx; /* gfx dividers */
unsigned long cm_clksel1_core; /* major subsystem dividers */
unsigned long cm_clksel1_pll; /* m,n */
unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
unsigned long base_sdrc_rfr; /* base refresh timing for a set */
unsigned short flags;
};
/* Core fields for cm_clksel, not ratio governed */
#define RX_CLKSEL_DSS1 (0x10 << 8)
#define RX_CLKSEL_DSS2 (0x0 << 13)
#define RX_CLKSEL_SSI (0x5 << 20)
/*-------------------------------------------------------------------------
* Voltage/DPLL ratios
*-------------------------------------------------------------------------*/
/* 2430 Ratio's, 2430-Ratio Config 1 */
#define R1_CLKSEL_L3 (4 << 0)
#define R1_CLKSEL_L4 (2 << 5)
#define R1_CLKSEL_USB (4 << 25)
#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
R1_CLKSEL_L4 | R1_CLKSEL_L3)
#define R1_CLKSEL_MPU (2 << 0)
#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
#define R1_CLKSEL_DSP (2 << 0)
#define R1_CLKSEL_DSP_IF (2 << 5)
#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
#define R1_CLKSEL_GFX (2 << 0)
#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
#define R1_CLKSEL_MDM (4 << 0)
#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
/* 2430-Ratio Config 2 */
#define R2_CLKSEL_L3 (6 << 0)
#define R2_CLKSEL_L4 (2 << 5)
#define R2_CLKSEL_USB (2 << 25)
#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
R2_CLKSEL_L4 | R2_CLKSEL_L3)
#define R2_CLKSEL_MPU (2 << 0)
#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
#define R2_CLKSEL_DSP (2 << 0)
#define R2_CLKSEL_DSP_IF (3 << 5)
#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
#define R2_CLKSEL_GFX (2 << 0)
#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
#define R2_CLKSEL_MDM (6 << 0)
#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
/* 2430-Ratio Bootm (BYPASS) */
#define RB_CLKSEL_L3 (1 << 0)
#define RB_CLKSEL_L4 (1 << 5)
#define RB_CLKSEL_USB (1 << 25)
#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
RB_CLKSEL_L4 | RB_CLKSEL_L3)
#define RB_CLKSEL_MPU (1 << 0)
#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
#define RB_CLKSEL_DSP (1 << 0)
#define RB_CLKSEL_DSP_IF (1 << 5)
#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
#define RB_CLKSEL_GFX (1 << 0)
#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
#define RB_CLKSEL_MDM (1 << 0)
#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
/* 2420 Ratio Equivalents */
#define RXX_CLKSEL_VLYNQ (0x12 << 15)
#define RXX_CLKSEL_SSI (0x8 << 20)
/* 2420-PRCM III 532MHz core */
#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
RIII_CLKSEL_L3)
#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
Annotation
- Detected declarations: `struct prcm_config`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.