arch/arm/mach-qcom/Kconfig
Source file repositories/reference/linux-study-clean/arch/arm/mach-qcom/Kconfig
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-qcom/Kconfig- Extension
[no extension]- Size
- 660 bytes
- Lines
- 25
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: build/configuration rule
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_QCOM
bool "Qualcomm Support"
depends on ARCH_MULTI_V7
select ARM_GIC
select ARM_AMBA
select CLKSRC_QCOM
select HAVE_ARM_ARCH_TIMER
select PINCTRL
select QCOM_SCM if SMP
help
Support for Qualcomm's devicetree based systems.
This includes support for a few devices with ARM64 SoC, that have
ARM32 signed firmware that does not allow booting ARM64 kernels.
if ARCH_QCOM
config ARCH_QCOM_RESERVE_SMEM
bool "Reserve SMEM at the beginning of RAM"
help
Reserve 2MB at the beginning of the System RAM for shared mem.
This is required on IPQ40xx, MSM8x60 and MSM8960 platforms.
endif
Annotation
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.