arch/arm/mach-s3c/regs-gpio-s3c64xx.h

Source file repositories/reference/linux-study-clean/arch/arm/mach-s3c/regs-gpio-s3c64xx.h

File Facts

System
Linux kernel
Corpus path
arch/arm/mach-s3c/regs-gpio-s3c64xx.h
Extension
.h
Size
7093 bytes
Lines
189
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__

/* Base addresses for each of the banks */

#define S3C64XX_GPIOREG(reg)	(S3C64XX_VA_GPIO + (reg))

#define S3C64XX_GPA_BASE	S3C64XX_GPIOREG(0x0000)
#define S3C64XX_GPB_BASE	S3C64XX_GPIOREG(0x0020)
#define S3C64XX_GPC_BASE	S3C64XX_GPIOREG(0x0040)
#define S3C64XX_GPD_BASE	S3C64XX_GPIOREG(0x0060)
#define S3C64XX_GPE_BASE	S3C64XX_GPIOREG(0x0080)
#define S3C64XX_GPF_BASE	S3C64XX_GPIOREG(0x00A0)
#define S3C64XX_GPG_BASE	S3C64XX_GPIOREG(0x00C0)
#define S3C64XX_GPH_BASE	S3C64XX_GPIOREG(0x00E0)
#define S3C64XX_GPI_BASE	S3C64XX_GPIOREG(0x0100)
#define S3C64XX_GPJ_BASE	S3C64XX_GPIOREG(0x0120)
#define S3C64XX_GPK_BASE	S3C64XX_GPIOREG(0x0800)
#define S3C64XX_GPL_BASE	S3C64XX_GPIOREG(0x0810)
#define S3C64XX_GPM_BASE	S3C64XX_GPIOREG(0x0820)
#define S3C64XX_GPN_BASE	S3C64XX_GPIOREG(0x0830)
#define S3C64XX_GPO_BASE	S3C64XX_GPIOREG(0x0140)
#define S3C64XX_GPP_BASE	S3C64XX_GPIOREG(0x0160)
#define S3C64XX_GPQ_BASE	S3C64XX_GPIOREG(0x0180)

/* SPCON */

#define S3C64XX_SPCON		S3C64XX_GPIOREG(0x1A0)

#define S3C64XX_SPCON_DRVCON_CAM_MASK		(0x3 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_SHIFT		(30)
#define S3C64XX_SPCON_DRVCON_CAM_2mA		(0x0 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_4mA		(0x1 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_7mA		(0x2 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_9mA		(0x3 << 30)

#define S3C64XX_SPCON_DRVCON_HSSPI_MASK		(0x3 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT	(28)
#define S3C64XX_SPCON_DRVCON_HSSPI_2mA		(0x0 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_4mA		(0x1 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_7mA		(0x2 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_9mA		(0x3 << 28)

#define S3C64XX_SPCON_DRVCON_HSMMC_MASK		(0x3 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT	(26)
#define S3C64XX_SPCON_DRVCON_HSMMC_2mA		(0x0 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_4mA		(0x1 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_7mA		(0x2 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_9mA		(0x3 << 26)

#define S3C64XX_SPCON_DRVCON_LCD_MASK		(0x3 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_SHIFT		(24)
#define S3C64XX_SPCON_DRVCON_LCD_2mA		(0x0 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_4mA		(0x1 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_7mA		(0x2 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_9mA		(0x3 << 24)

#define S3C64XX_SPCON_DRVCON_MODEM_MASK		(0x3 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT	(22)
#define S3C64XX_SPCON_DRVCON_MODEM_2mA		(0x0 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_4mA		(0x1 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_7mA		(0x2 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_9mA		(0x3 << 22)

#define S3C64XX_SPCON_nRSTOUT_OEN		(1 << 21)

#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK	(0x3 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT	(18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA	(0x0 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA	(0x1 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA	(0x2 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA	(0x3 << 18)

#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK		(0x3 << 16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT	(16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED	(0x0 << 16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN		(0x1 << 16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_UP		(0x2 << 16)

#define S3C64XX_SPCON_MEM1_D_PUD1_MASK		(0x3 << 14)
#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT		(14)
#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED	(0x0 << 14)
#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN		(0x1 << 14)
#define S3C64XX_SPCON_MEM1_D_PUD1_UP		(0x2 << 14)

#define S3C64XX_SPCON_MEM1_D_PUD0_MASK		(0x3 << 12)
#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT		(12)
#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED	(0x0 << 12)
#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN		(0x1 << 12)
#define S3C64XX_SPCON_MEM1_D_PUD0_UP		(0x2 << 12)

Annotation

Implementation Notes