arch/arm/mach-tegra/reset-handler.S
Source file repositories/reference/linux-study-clean/arch/arm/mach-tegra/reset-handler.S
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mach-tegra/reset-handler.S- Extension
.S- Size
- 7121 bytes
- Lines
- 304
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: arch/arm
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
linux/init.hlinux/linkage.hsoc/tegra/flowctrl.hsoc/tegra/fuse.hasm/assembler.hasm/asm-offsets.hasm/cache.hiomap.hreset.hsleep.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <linux/init.h>
#include <linux/linkage.h>
#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include "iomap.h"
#include "reset.h"
#include "sleep.h"
#define PMC_SCRATCH41 0x140
.arch armv7-a
#ifdef CONFIG_PM_SLEEP
/*
* tegra_resume
*
* CPU boot vector when restarting the a CPU following
* an LP2 transition. Also branched to by LP0 and LP1 resume after
* re-enabling sdram.
*
* r6: SoC ID
* r8: CPU part number
*/
ENTRY(tegra_resume)
check_cpu_part_num 0xc09, r8, r9
bleq v7_invalidate_l1
cpu_id r0
cmp r0, #0 @ CPU0?
THUMB( it ne )
bne cpu_resume @ no
tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
/* Are we on Tegra20? */
cmp r6, #TEGRA20
beq 1f @ Yes
/* Clear the flow controller flags for this CPU. */
cpu_to_csr_reg r3, r0
mov32 r2, TEGRA_FLOW_CTRL_BASE
ldr r1, [r2, r3]
/* Clear event & intr flag */
orr r1, r1, \
#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps
@ & ext flags for CPU power mgnt
bic r1, r1, r0
str r1, [r2, r3]
1:
mov32 r9, 0xc09
cmp r8, r9
bne end_ca9_scu_l2_resume
#ifdef CONFIG_HAVE_ARM_SCU
/* enable SCU */
mov32 r0, TEGRA_ARM_PERIF_BASE
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
#endif
bl tegra_resume_trusted_foundations
#ifdef CONFIG_CACHE_L2X0
/* L2 cache resume & re-enable */
bl l2c310_early_resume
Annotation
- Immediate include surface: `linux/init.h`, `linux/linkage.h`, `soc/tegra/flowctrl.h`, `soc/tegra/fuse.h`, `asm/assembler.h`, `asm/asm-offsets.h`, `asm/cache.h`, `iomap.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.