arch/arm/mach-tegra/sleep.S

Source file repositories/reference/linux-study-clean/arch/arm/mach-tegra/sleep.S

File Facts

System
Linux kernel
Corpus path
arch/arm/mach-tegra/sleep.S
Extension
.S
Size
3281 bytes
Lines
153
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: arch/arm
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/linkage.h>

#include <asm/assembler.h>
#include <asm/cache.h>
#include <asm/cp15.h>
#include <asm/hardware/cache-l2x0.h>

#include "iomap.h"
#include "sleep.h"

#define CLK_RESET_CCLK_BURST	0x20
#define CLK_RESET_CCLK_DIVIDER  0x24

.arch armv7-a

#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
/*
 * tegra_disable_clean_inv_dcache
 *
 * disable, clean & invalidate the D-cache
 *
 * Corrupted registers: r1-r3, r6, r8, r9-r11
 */
ENTRY(tegra_disable_clean_inv_dcache)
	stmfd	sp!, {r0, r4-r5, r7, r9-r11, lr}
	dmb					@ ensure ordering

	/* Disable the D-cache */
	mrc	p15, 0, r2, c1, c0, 0
	tst	r2, #CR_C			@ see tegra_sleep_cpu()
	bic	r2, r2, #CR_C
	mcrne	p15, 0, r2, c1, c0, 0
	isb

	/* Flush the D-cache */
	cmp	r0, #TEGRA_FLUSH_CACHE_ALL
	blne	v7_flush_dcache_louis
	bleq	v7_flush_dcache_all

	/* Trun off coherency */
	exit_smp r4, r5

	ldmfd	sp!, {r0, r4-r5, r7, r9-r11, pc}
ENDPROC(tegra_disable_clean_inv_dcache)
#endif

#ifdef CONFIG_PM_SLEEP
/*
 * tegra_init_l2_for_a15
 *
 * set up the correct L2 cache data RAM latency
 */
ENTRY(tegra_init_l2_for_a15)
	mrc	p15, 0, r0, c0, c0, 5
	ubfx	r0, r0, #8, #4
	tst	r0, #1				@ only need for cluster 0
	bne	_exit_init_l2_a15

	mrc	p15, 0x1, r0, c9, c0, 2
	and	r0, r0, #7
	cmp	r0, #2
	bicne	r0, r0, #7
	orrne	r0, r0, #2
	mcrne	p15, 0x1, r0, c9, c0, 2
_exit_init_l2_a15:

	ret	lr
ENDPROC(tegra_init_l2_for_a15)

/*

Annotation

Implementation Notes