arch/arm/mach-tegra/sleep-tegra30.S

Source file repositories/reference/linux-study-clean/arch/arm/mach-tegra/sleep-tegra30.S

File Facts

System
Linux kernel
Corpus path
arch/arm/mach-tegra/sleep-tegra30.S
Extension
.S
Size
23756 bytes
Lines
910
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: arch/arm
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/linkage.h>

#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>

#include <asm/asm-offsets.h>
#include <asm/assembler.h>
#include <asm/cache.h>

#include "irammap.h"
#include "sleep.h"

#define EMC_CFG				0xc
#define EMC_ADR_CFG			0x10
#define EMC_TIMING_CONTROL		0x28
#define EMC_NOP				0xdc
#define EMC_SELF_REF			0xe0
#define EMC_MRW				0xe8
#define EMC_FBIO_CFG5			0x104
#define EMC_AUTO_CAL_CONFIG		0x2a4
#define EMC_AUTO_CAL_INTERVAL		0x2a8
#define EMC_AUTO_CAL_STATUS		0x2ac
#define EMC_REQ_CTRL			0x2b0
#define EMC_CFG_DIG_DLL			0x2bc
#define EMC_EMC_STATUS			0x2b4
#define EMC_ZCAL_INTERVAL		0x2e0
#define EMC_ZQ_CAL			0x2ec
#define EMC_XM2VTTGENPADCTRL		0x310
#define EMC_XM2VTTGENPADCTRL2		0x314

#define PMC_CTRL			0x0
#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */

#define PMC_PLLP_WB0_OVERRIDE		0xf8
#define PMC_IO_DPD_REQ			0x1b8
#define PMC_IO_DPD_STATUS		0x1bc

#define CLK_RESET_CCLK_BURST		0x20
#define CLK_RESET_CCLK_DIVIDER		0x24
#define CLK_RESET_SCLK_BURST		0x28
#define CLK_RESET_SCLK_DIVIDER		0x2c

#define CLK_RESET_PLLC_BASE		0x80
#define CLK_RESET_PLLC_MISC		0x8c
#define CLK_RESET_PLLM_BASE		0x90
#define CLK_RESET_PLLM_MISC		0x9c
#define CLK_RESET_PLLP_BASE		0xa0
#define CLK_RESET_PLLP_MISC		0xac
#define CLK_RESET_PLLA_BASE		0xb0
#define CLK_RESET_PLLA_MISC		0xbc
#define CLK_RESET_PLLX_BASE		0xe0
#define CLK_RESET_PLLX_MISC		0xe4
#define CLK_RESET_PLLX_MISC3		0x518
#define CLK_RESET_PLLX_MISC3_IDDQ	3
#define CLK_RESET_PLLM_MISC_IDDQ	5
#define CLK_RESET_PLLC_MISC_IDDQ	26
#define CLK_RESET_PLLP_RESHIFT		0x528
#define CLK_RESET_PLLP_RESHIFT_DEFAULT	0x3b
#define CLK_RESET_PLLP_RESHIFT_ENABLE	0x3

#define CLK_RESET_CLK_SOURCE_MSELECT	0x3b4

#define MSELECT_CLKM			(0x3 << 30)

#define LOCK_DELAY 50 /* safety delay after lock is detected */

#define TEGRA30_POWER_HOTPLUG_SHUTDOWN	(1 << 27) /* Hotplug shutdown */

#define PLLA_STORE_MASK			(1 << 0)
#define PLLC_STORE_MASK			(1 << 1)

Annotation

Implementation Notes