arch/arm/mm/cache.c
Source file repositories/reference/linux-study-clean/arch/arm/mm/cache.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mm/cache.c- Extension
.c- Size
- 28007 bytes
- Lines
- 664
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hasm/cacheflush.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* This file defines C prototypes for the low-level cache assembly functions
* and populates a vtable for each selected ARM CPU cache type.
*/
#include <linux/types.h>
#include <asm/cacheflush.h>
#ifdef CONFIG_CPU_CACHE_V4
void v4_flush_icache_all(void);
void v4_flush_kern_cache_all(void);
void v4_flush_user_cache_all(void);
void v4_flush_user_cache_range(unsigned long, unsigned long, unsigned int);
void v4_coherent_kern_range(unsigned long, unsigned long);
int v4_coherent_user_range(unsigned long, unsigned long);
void v4_flush_kern_dcache_area(void *, size_t);
void v4_dma_map_area(const void *, size_t, int);
void v4_dma_unmap_area(const void *, size_t, int);
void v4_dma_flush_range(const void *, const void *);
struct cpu_cache_fns v4_cache_fns __initconst = {
.flush_icache_all = v4_flush_icache_all,
.flush_kern_all = v4_flush_kern_cache_all,
.flush_kern_louis = v4_flush_kern_cache_all,
.flush_user_all = v4_flush_user_cache_all,
.flush_user_range = v4_flush_user_cache_range,
.coherent_kern_range = v4_coherent_kern_range,
.coherent_user_range = v4_coherent_user_range,
.flush_kern_dcache_area = v4_flush_kern_dcache_area,
.dma_map_area = v4_dma_map_area,
.dma_unmap_area = v4_dma_unmap_area,
.dma_flush_range = v4_dma_flush_range,
};
#endif
/* V4 write-back cache "V4WB" */
#ifdef CONFIG_CPU_CACHE_V4WB
void v4wb_flush_icache_all(void);
void v4wb_flush_kern_cache_all(void);
void v4wb_flush_user_cache_all(void);
void v4wb_flush_user_cache_range(unsigned long, unsigned long, unsigned int);
void v4wb_coherent_kern_range(unsigned long, unsigned long);
int v4wb_coherent_user_range(unsigned long, unsigned long);
void v4wb_flush_kern_dcache_area(void *, size_t);
void v4wb_dma_map_area(const void *, size_t, int);
void v4wb_dma_unmap_area(const void *, size_t, int);
void v4wb_dma_flush_range(const void *, const void *);
struct cpu_cache_fns v4wb_cache_fns __initconst = {
.flush_icache_all = v4wb_flush_icache_all,
.flush_kern_all = v4wb_flush_kern_cache_all,
.flush_kern_louis = v4wb_flush_kern_cache_all,
.flush_user_all = v4wb_flush_user_cache_all,
.flush_user_range = v4wb_flush_user_cache_range,
.coherent_kern_range = v4wb_coherent_kern_range,
.coherent_user_range = v4wb_coherent_user_range,
.flush_kern_dcache_area = v4wb_flush_kern_dcache_area,
.dma_map_area = v4wb_dma_map_area,
.dma_unmap_area = v4wb_dma_unmap_area,
.dma_flush_range = v4wb_dma_flush_range,
};
#endif
/* V4 write-through cache "V4WT" */
#ifdef CONFIG_CPU_CACHE_V4WT
void v4wt_flush_icache_all(void);
void v4wt_flush_kern_cache_all(void);
void v4wt_flush_user_cache_all(void);
void v4wt_flush_user_cache_range(unsigned long, unsigned long, unsigned int);
void v4wt_coherent_kern_range(unsigned long, unsigned long);
int v4wt_coherent_user_range(unsigned long, unsigned long);
void v4wt_flush_kern_dcache_area(void *, size_t);
void v4wt_dma_map_area(const void *, size_t, int);
void v4wt_dma_unmap_area(const void *, size_t, int);
void v4wt_dma_flush_range(const void *, const void *);
struct cpu_cache_fns v4wt_cache_fns __initconst = {
.flush_icache_all = v4wt_flush_icache_all,
.flush_kern_all = v4wt_flush_kern_cache_all,
.flush_kern_louis = v4wt_flush_kern_cache_all,
.flush_user_all = v4wt_flush_user_cache_all,
.flush_user_range = v4wt_flush_user_cache_range,
.coherent_kern_range = v4wt_coherent_kern_range,
.coherent_user_range = v4wt_coherent_user_range,
.flush_kern_dcache_area = v4wt_flush_kern_dcache_area,
.dma_map_area = v4wt_dma_map_area,
.dma_unmap_area = v4wt_dma_unmap_area,
.dma_flush_range = v4wt_dma_flush_range,
};
Annotation
- Immediate include surface: `linux/types.h`, `asm/cacheflush.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.