arch/arm/mm/cache-tauros3.h

File Facts

System

Linux kernel

Corpus path

arch/arm/mm/cache-tauros3.h

Extension

.h

Size

771 bytes

Lines

30

Domain

Architecture Layer

Bucket

arch/arm

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __ASM_ARM_HARDWARE_TAUROS3_H
#define __ASM_ARM_HARDWARE_TAUROS3_H

/*
 * Marvell Tauros3 L2CC is compatible with PL310 r0p0
 * but with PREFETCH_CTRL (r2p0) and an additional event counter.
 * Also, there is AUX2_CTRL for some Marvell specific control.
 */

#define TAUROS3_EVENT_CNT2_CFG		0x224
#define TAUROS3_EVENT_CNT2_VAL		0x228
#define TAUROS3_INV_ALL			0x780
#define TAUROS3_CLEAN_ALL		0x784
#define TAUROS3_AUX2_CTRL		0x820

/* Registers shifts and masks */
#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN	(1 << 2)

#endif

Annotation

• Atlas domain: Architecture Layer / arch/arm.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.