arch/arm/mm/cache-v6.S
Source file repositories/reference/linux-study-clean/arch/arm/mm/cache-v6.S
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mm/cache-v6.S- Extension
.S- Size
- 7300 bytes
- Lines
- 303
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: arch/arm
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/linkage.hlinux/init.hlinux/cfi_types.hasm/assembler.hasm/errno.hasm/unwind.hproc-macros.S
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/cfi_types.h>
#include <asm/assembler.h>
#include <asm/errno.h>
#include <asm/unwind.h>
#include "proc-macros.S"
#define HARVARD_CACHE
#define CACHE_LINE_SIZE 32
#define D_CACHE_LINE_SIZE 32
#define BTB_FLUSH_SIZE 8
.arch armv6
/*
* v6_flush_icache_all()
*
* Flush the whole I-cache.
*
* ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
* This erratum is present in 1136, 1156 and 1176. It does not affect the
* MPCore.
*
* Registers:
* r0 - set to 0
* r1 - corrupted
*/
SYM_TYPED_FUNC_START(v6_flush_icache_all)
mov r0, #0
#ifdef CONFIG_ARM_ERRATA_411920
mrs r1, cpsr
cpsid ifa @ disable interrupts
mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
msr cpsr_cx, r1 @ restore interrupts
.rept 11 @ ARM Ltd recommends at least
nop @ 11 NOPs
.endr
#else
mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
#endif
ret lr
SYM_FUNC_END(v6_flush_icache_all)
/*
* v6_flush_cache_all()
*
* Flush the entire cache.
*
* It is assumed that:
*/
SYM_TYPED_FUNC_START(v6_flush_kern_cache_all)
mov r0, #0
#ifdef HARVARD_CACHE
mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
#ifndef CONFIG_ARM_ERRATA_411920
mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
#else
b v6_flush_icache_all
#endif
#else
mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
#endif
ret lr
SYM_FUNC_END(v6_flush_kern_cache_all)
Annotation
- Immediate include surface: `linux/linkage.h`, `linux/init.h`, `linux/cfi_types.h`, `asm/assembler.h`, `asm/errno.h`, `asm/unwind.h`, `proc-macros.S`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.