arch/arm/mm/cache-v7m.S

Source file repositories/reference/linux-study-clean/arch/arm/mm/cache-v7m.S

File Facts

System
Linux kernel
Corpus path
arch/arm/mm/cache-v7m.S
Extension
.S
Size
10479 bytes
Lines
452
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: arch/arm
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/cfi_types.h>
#include <asm/assembler.h>
#include <asm/errno.h>
#include <asm/unwind.h>
#include <asm/v7m.h>

#include "proc-macros.S"

.arch armv7-m

/* Generic V7M read/write macros for memory mapped cache operations */
.macro v7m_cache_read, rt, reg
	movw	\rt, #:lower16:BASEADDR_V7M_SCB + \reg
	movt	\rt, #:upper16:BASEADDR_V7M_SCB + \reg
	ldr     \rt, [\rt]
.endm

.macro v7m_cacheop, rt, tmp, op, c = al
	movw\c	\tmp, #:lower16:BASEADDR_V7M_SCB + \op
	movt\c	\tmp, #:upper16:BASEADDR_V7M_SCB + \op
	str\c	\rt, [\tmp]
.endm


.macro	read_ccsidr, rt
	v7m_cache_read \rt, V7M_SCB_CCSIDR
.endm

.macro read_clidr, rt
	v7m_cache_read \rt, V7M_SCB_CLIDR
.endm

.macro	write_csselr, rt, tmp
	v7m_cacheop \rt, \tmp, V7M_SCB_CSSELR
.endm

/*
 * dcisw: Invalidate data cache by set/way
 */
.macro dcisw, rt, tmp
	v7m_cacheop \rt, \tmp, V7M_SCB_DCISW
.endm

/*
 * dccisw: Clean and invalidate data cache by set/way
 */
.macro dccisw, rt, tmp
	v7m_cacheop \rt, \tmp, V7M_SCB_DCCISW
.endm

/*
 * dccimvac: Clean and invalidate data cache line by MVA to PoC.
 */
.irp    c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
.macro dccimvac\c, rt, tmp
	v7m_cacheop \rt, \tmp, V7M_SCB_DCCIMVAC, \c
.endm
.endr

/*
 * dcimvac: Invalidate data cache line by MVA to PoC
 */
.irp    c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
.macro dcimvac\c, rt, tmp
	v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c
.endm
.endr

Annotation

Implementation Notes