arch/arm/mm/copypage-xscale.c
Source file repositories/reference/linux-study-clean/arch/arm/mm/copypage-xscale.c
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mm/copypage-xscale.c- Extension
.c- Size
- 3626 bytes
- Lines
- 135
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/mm.hlinux/highmem.hlinux/pagemap.hasm/tlbflush.hasm/cacheflush.hmm.h
Detected Declarations
function mc_copy_user_pagefunction xscale_mc_copy_user_highpagefunction xscale_mc_clear_user_highpage
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/lib/copypage-xscale.S
*
* Copyright (C) 1995-2005 Russell King
*
* This handles the mini data cache, as found on SA11x0 and XScale
* processors. When we copy a user page page, we map it in such a way
* that accesses to this page will not touch the main data cache, but
* will be cached in the mini data cache. This prevents us thrashing
* the main data cache on page faults.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/pagemap.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
#include "mm.h"
#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
L_PTE_MT_MINICACHE)
static DEFINE_RAW_SPINLOCK(minicache_lock);
/*
* XScale mini-dcache optimised copy_user_highpage
*
* We flush the destination cache lines just before we write the data into the
* corresponding address. Since the Dcache is read-allocate, this removes the
* Dcache aliasing issue. The writes will be forwarded to the write buffer,
* and merged as appropriate.
*/
static void mc_copy_user_page(void *from, void *to)
{
int tmp;
/*
* Strangely enough, best performance is achieved
* when prefetching destination as well. (NP)
*/
asm volatile ("\
.arch xscale \n\
pld [%0, #0] \n\
pld [%0, #32] \n\
pld [%1, #0] \n\
pld [%1, #32] \n\
1: pld [%0, #64] \n\
pld [%0, #96] \n\
pld [%1, #64] \n\
pld [%1, #96] \n\
2: ldrd r2, r3, [%0], #8 \n\
ldrd r4, r5, [%0], #8 \n\
mov ip, %1 \n\
strd r2, r3, [%1], #8 \n\
ldrd r2, r3, [%0], #8 \n\
strd r4, r5, [%1], #8 \n\
ldrd r4, r5, [%0], #8 \n\
strd r2, r3, [%1], #8 \n\
strd r4, r5, [%1], #8 \n\
mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
ldrd r2, r3, [%0], #8 \n\
mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
ldrd r4, r5, [%0], #8 \n\
mov ip, %1 \n\
strd r2, r3, [%1], #8 \n\
ldrd r2, r3, [%0], #8 \n\
strd r4, r5, [%1], #8 \n\
ldrd r4, r5, [%0], #8 \n\
strd r2, r3, [%1], #8 \n\
strd r4, r5, [%1], #8 \n\
mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
subs %2, %2, #1 \n\
mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
bgt 1b \n\
beq 2b "
: "+&r" (from), "+&r" (to), "=&r" (tmp)
: "2" (PAGE_SIZE / 64 - 1)
: "r2", "r3", "r4", "r5", "ip");
}
void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
unsigned long vaddr, struct vm_area_struct *vma)
{
struct folio *src = page_folio(from);
void *kto = kmap_atomic(to);
if (!test_and_set_bit(PG_dcache_clean, &src->flags.f))
Annotation
- Immediate include surface: `linux/init.h`, `linux/mm.h`, `linux/highmem.h`, `linux/pagemap.h`, `asm/tlbflush.h`, `asm/cacheflush.h`, `mm.h`.
- Detected declarations: `function mc_copy_user_page`, `function xscale_mc_copy_user_highpage`, `function xscale_mc_clear_user_highpage`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.