arch/arm/mm/proc-v6.S
Source file repositories/reference/linux-study-clean/arch/arm/mm/proc-v6.S
File Facts
- System
- Linux kernel
- Corpus path
arch/arm/mm/proc-v6.S- Extension
.S- Size
- 8661 bytes
- Lines
- 307
- Domain
- Architecture Layer
- Bucket
- arch/arm
- Inferred role
- Architecture Layer: arch/arm
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/cfi_types.hlinux/linkage.hlinux/pgtable.hasm/assembler.hasm/asm-offsets.hasm/hwcap.hasm/pgtable-hwdef.hproc-macros.S
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <linux/init.h>
#include <linux/cfi_types.h>
#include <linux/linkage.h>
#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include "proc-macros.S"
#define D_CACHE_LINE_SIZE 32
#define TTB_C (1 << 0)
#define TTB_S (1 << 1)
#define TTB_IMP (1 << 2)
#define TTB_RGN_NC (0 << 3)
#define TTB_RGN_WBWA (1 << 3)
#define TTB_RGN_WT (2 << 3)
#define TTB_RGN_WB (3 << 3)
#define TTB_FLAGS_UP TTB_RGN_WBWA
#define PMD_FLAGS_UP PMD_SECT_WB
#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
.arch armv6
SYM_TYPED_FUNC_START(cpu_v6_proc_init)
ret lr
SYM_FUNC_END(cpu_v6_proc_init)
SYM_TYPED_FUNC_START(cpu_v6_proc_fin)
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x0006 @ .............ca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches
ret lr
SYM_FUNC_END(cpu_v6_proc_fin)
/*
* cpu_v6_reset(loc)
*
* Perform a soft reset of the system. Put the CPU into the
* same state as it would be if it had been reset, and branch
* to what would be the reset vector.
*
* - loc - location to jump to for soft reset
*/
.align 5
.pushsection .idmap.text, "ax"
SYM_TYPED_FUNC_START(cpu_v6_reset)
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x1 @ ...............m
mcr p15, 0, r1, c1, c0, 0 @ disable MMU
mov r1, #0
mcr p15, 0, r1, c7, c5, 4 @ ISB
ret r0
SYM_FUNC_END(cpu_v6_reset)
.popsection
/*
* cpu_v6_do_idle()
*
* Idle the processor (eg, wait for interrupt).
*
* IRQs are already disabled.
*/
SYM_TYPED_FUNC_START(cpu_v6_do_idle)
mov r1, #0
Annotation
- Immediate include surface: `linux/init.h`, `linux/cfi_types.h`, `linux/linkage.h`, `linux/pgtable.h`, `asm/assembler.h`, `asm/asm-offsets.h`, `asm/hwcap.h`, `asm/pgtable-hwdef.h`.
- Atlas domain: Architecture Layer / arch/arm.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.