arch/arm/net/bpf_jit_32.h

Source file repositories/reference/linux-study-clean/arch/arm/net/bpf_jit_32.h

File Facts

System
Linux kernel
Corpus path
arch/arm/net/bpf_jit_32.h
Extension
.h
Size
9821 bytes
Lines
281
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef PFILTER_OPCODES_ARM_H
#define PFILTER_OPCODES_ARM_H

/* ARM 32bit Registers */
#define ARM_R0	0
#define ARM_R1	1
#define ARM_R2	2
#define ARM_R3	3
#define ARM_R4	4
#define ARM_R5	5
#define ARM_R6	6
#define ARM_R7	7
#define ARM_R8	8
#define ARM_R9	9
#define ARM_R10	10
#define ARM_FP	11	/* Frame Pointer */
#define ARM_IP	12	/* Intra-procedure scratch register */
#define ARM_SP	13	/* Stack pointer: as load/store base reg */
#define ARM_LR	14	/* Link Register */
#define ARM_PC	15	/* Program counter */

#define ARM_COND_EQ		0x0	/* == */
#define ARM_COND_NE		0x1	/* != */
#define ARM_COND_CS		0x2	/* unsigned >= */
#define ARM_COND_HS		ARM_COND_CS
#define ARM_COND_CC		0x3	/* unsigned < */
#define ARM_COND_LO		ARM_COND_CC
#define ARM_COND_MI		0x4	/* < 0 */
#define ARM_COND_PL		0x5	/* >= 0 */
#define ARM_COND_VS		0x6	/* Signed Overflow */
#define ARM_COND_VC		0x7	/* No Signed Overflow */
#define ARM_COND_HI		0x8	/* unsigned > */
#define ARM_COND_LS		0x9	/* unsigned <= */
#define ARM_COND_GE		0xa	/* Signed >= */
#define ARM_COND_LT		0xb	/* Signed < */
#define ARM_COND_GT		0xc	/* Signed > */
#define ARM_COND_LE		0xd	/* Signed <= */
#define ARM_COND_AL		0xe	/* None */

/* register shift types */
#define SRTYPE_LSL		0
#define SRTYPE_LSR		1
#define SRTYPE_ASR		2
#define SRTYPE_ROR		3
#define SRTYPE_ASL		(SRTYPE_LSL)

#define ARM_INST_ADD_R		0x00800000
#define ARM_INST_ADDS_R		0x00900000
#define ARM_INST_ADC_R		0x00a00000
#define ARM_INST_ADC_I		0x02a00000
#define ARM_INST_ADD_I		0x02800000
#define ARM_INST_ADDS_I		0x02900000

#define ARM_INST_AND_R		0x00000000
#define ARM_INST_ANDS_R		0x00100000
#define ARM_INST_AND_I		0x02000000

#define ARM_INST_BIC_R		0x01c00000
#define ARM_INST_BIC_I		0x03c00000

#define ARM_INST_B		0x0a000000
#define ARM_INST_BX		0x012FFF10
#define ARM_INST_BLX_R		0x012fff30

#define ARM_INST_CMP_R		0x01500000
#define ARM_INST_CMP_I		0x03500000

#define ARM_INST_EOR_R		0x00200000
#define ARM_INST_EOR_I		0x02200000

#define ARM_INST_LDST__U	0x00800000
#define ARM_INST_LDST__IMM12	0x00000fff
#define ARM_INST_LDRB_I		0x05500000
#define ARM_INST_LDRB_R		0x07d00000
#define ARM_INST_LDRSB_I	0x015000d0
#define ARM_INST_LDRD_I		0x014000d0
#define ARM_INST_LDRH_I		0x015000b0
#define ARM_INST_LDRH_R		0x019000b0
#define ARM_INST_LDRSH_I	0x015000f0
#define ARM_INST_LDR_I		0x05100000
#define ARM_INST_LDR_R		0x07900000

#define ARM_INST_LDM		0x08900000
#define ARM_INST_LDM_IA		0x08b00000

#define ARM_INST_LSL_I		0x01a00000
#define ARM_INST_LSL_R		0x01a00010

#define ARM_INST_LSR_I		0x01a00020
#define ARM_INST_LSR_R		0x01a00030

Annotation

Implementation Notes