arch/arm/nwfpe/fpopcode.h

Source file repositories/reference/linux-study-clean/arch/arm/nwfpe/fpopcode.h

File Facts

System
Linux kernel
Corpus path
arch/arm/nwfpe/fpopcode.h
Extension
.h
Size
14789 bytes
Lines
470
Domain
Architecture Layer
Bucket
arch/arm
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

NetWinder Floating Point Emulator
    (c) Rebel.COM, 1998,1999
    (c) Philip Blundell, 2001

    Direct questions, comments to Scott Bambrough <scottb@netwinder.org>

*/

#ifndef __FPOPCODE_H__
#define __FPOPCODE_H__


/*
ARM Floating Point Instruction Classes
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 
|c o n d|1 1 0 P|U|u|W|L|   Rn  |v|  Fd |0|0|0|1|  o f f s e t  | CPDT
|c o n d|1 1 0 P|U|w|W|L|   Rn  |x|  Fd |0|0|1|0|  o f f s e t  | CPDT (copro 2)
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 
|c o n d|1 1 1 0|a|b|c|d|e|  Fn |j|  Fd |0|0|0|1|f|g|h|0|i|  Fm | CPDO
|c o n d|1 1 1 0|a|b|c|L|e|  Fn |   Rd  |0|0|0|1|f|g|h|1|i|  Fm | CPRT
|c o n d|1 1 1 0|a|b|c|1|e|  Fn |1|1|1|1|0|0|0|1|f|g|h|1|i|  Fm | comparisons
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 

CPDT		data transfer instructions
		LDF, STF, LFM (copro 2), SFM (copro 2)
		
CPDO		dyadic arithmetic instructions
		ADF, MUF, SUF, RSF, DVF, RDF,
		POW, RPW, RMF, FML, FDV, FRD, POL

CPDO		monadic arithmetic instructions
		MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
		SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
		
CPRT		joint arithmetic/data transfer instructions
		FIX (arithmetic followed by load/store)
		FLT (load/store followed by arithmetic)
		CMF, CNF CMFE, CNFE (comparisons)
		WFS, RFS (write/read floating point status register)
		WFC, RFC (write/read floating point control register)

cond		condition codes
P		pre/post index bit: 0 = postindex, 1 = preindex
U		up/down bit: 0 = stack grows down, 1 = stack grows up
W		write back bit: 1 = update base register (Rn)
L		load/store bit: 0 = store, 1 = load
Rn		base register
Rd		destination/source register		
Fd		floating point destination register
Fn		floating point source register
Fm		floating point source register or floating point constant

uv		transfer length (TABLE 1)
wx		register count (TABLE 2)
abcd		arithmetic opcode (TABLES 3 & 4)
ef		destination size (rounding precision) (TABLE 5)
gh		rounding mode (TABLE 6)
j		dyadic/monadic bit: 0 = dyadic, 1 = monadic
i 		constant bit: 1 = constant (TABLE 6)
*/

/*
TABLE 1
+-------------------------+---+---+---------+---------+
|  Precision              | u | v | FPSR.EP | length  |
+-------------------------+---+---+---------+---------+
| Single                  | 0 | 0 |    x    | 1 words |
| Double                  | 1 | 1 |    x    | 2 words |
| Extended                | 1 | 1 |    x    | 3 words |
| Packed decimal          | 1 | 1 |    0    | 3 words |
| Expanded packed decimal | 1 | 1 |    1    | 4 words |
+-------------------------+---+---+---------+---------+
Note: x = don't care
*/

/*
TABLE 2
+---+---+---------------------------------+
| w | x | Number of registers to transfer |
+---+---+---------------------------------+
| 0 | 1 |  1                              |
| 1 | 0 |  2                              |
| 1 | 1 |  3                              |
| 0 | 0 |  4                              |
+---+---+---------------------------------+
*/

/*
TABLE 3: Dyadic Floating Point Opcodes
+---+---+---+---+----------+-----------------------+-----------------------+

Annotation

Implementation Notes