arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
Extension
.dts
Size
2756 bytes
Lines
137
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright Altera Corporation (C) 2015. All rights reserved.
 */

#include "socfpga_stratix10_socdk.dtsi"

/ {
	model = "SoCFPGA Stratix 10 SoCDK";
	compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
};

&pinctrl0 {
	i2c1_pmx_func: i2c1-pmx-func-pins {
		pinctrl-single,pins = <
			0x78   0x4   /* I2C1_SDA (IO6-B) PIN30SEL) */
			0x7c   0x4   /* I2C1_SCL (IO7-B) PIN31SEL */
		>;
	};

	i2c1_pmx_func_gpio: i2c1-pmx-func-gpio-pins {
		pinctrl-single,pins = <
			0x78   0x8   /* I2C1_SDA (IO6-B) PIN30SEL) */
			0x7c   0x8   /* I2C1_SCL (IO7-B) PIN31SEL */
		>;
	};
};

&gmac0 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&phy0>;

	max-frame-size = <9000>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@4 {
			reg = <4>;

			txd0-skew-ps = <0>; /* -420ps */
			txd1-skew-ps = <0>; /* -420ps */
			txd2-skew-ps = <0>; /* -420ps */
			txd3-skew-ps = <0>; /* -420ps */
			rxd0-skew-ps = <420>; /* 0ps */
			rxd1-skew-ps = <420>; /* 0ps */
			rxd2-skew-ps = <420>; /* 0ps */
			rxd3-skew-ps = <420>; /* 0ps */
			txen-skew-ps = <0>; /* -420ps */
			txc-skew-ps = <900>; /* 0ps */
			rxdv-skew-ps = <420>; /* 0ps */
			rxc-skew-ps = <1680>; /* 780ps */
		};
	};
};

&mmc {
	status = "okay";
	cap-sd-highspeed;
	cap-mmc-highspeed;
	broken-cd;
	bus-width = <4>;
	clk-phase-sd-hs = <0>, <135>;
};

&i2c1 {
	status = "okay";
	clock-frequency = <100000>;

Annotation

Implementation Notes