arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts
Extension
.dts
Size
1512 bytes
Lines
106
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022, Intel Corporation
 */

#include "socfpga_stratix10.dtsi"

/ {
	model = "SOCFPGA Stratix 10 SWVP";
	compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;

		timer0 = &timer0;
		timer1 = &timer1;
		timer2 = &timer2;
		timer3 = &timer3;

		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		ethernet2 = &gmac2;
	};

	chosen {
		stdout-path = "serial1:115200n8";
		linux,initrd-start = <0x10000000>;
		linux,initrd-end = <0x125c8324>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};
};

&cpu0 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x0000fff8>;
};

&cpu1 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x0000fff8>;
};

&cpu2 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x0000fff8>;
};

&cpu3 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x0000fff8>;
};

&osc1 {
	clock-frequency = <25000000>;
};

&gmac0 {
	status = "okay";
	phy-mode = "rgmii";
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";
};

Annotation

Implementation Notes