arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
Extension
.dtsi
Size
4141 bytes
Lines
225
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0

/ {
	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};
				core1 {
					cpu = <&CPU3>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&CPU4>;
				};
				core1 {
					cpu = <&CPU5>;
				};
			};
			cluster3 {
				core0 {
					cpu = <&CPU6>;
				};
				core1 {
					cpu = <&CPU7>;
				};
			};
		};

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_0>;

		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x1>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;

Annotation

Implementation Notes