arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi- Extension
.dtsi- Size
- 7276 bytes
- Lines
- 284
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* DTS file for AMD Seattle SoC
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*/
/ {
compatible = "amd,seattle";
interrupt-parent = <&gic0>;
#address-cells = <2>;
#size-cells = <2>;
/include/ "amd-seattle-clks.dtsi"
gic0: interrupt-controller@e1101000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0xe1110000 0 0x1000>,
<0x0 0xe112f000 0 0x2000>,
<0x0 0xe1140000 0 0x2000>,
<0x0 0xe1160000 0 0x2000>;
interrupts = <1 9 0xf04>;
ranges = <0 0 0 0xe1100000 0 0x100000>;
v2m0: v2m@e0080000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x00080000 0 0x1000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff04>,
<1 14 0xff04>,
<1 11 0xff04>,
<1 10 0xff04>;
};
smb0: bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* dma-ranges is 40-bit address space containing:
* - GICv2m MSI register is at 0xe0080000
* - DRAM range [0x8000000000 to 0xffffffffff]
*/
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
sata0: sata@e0300000 {
compatible = "snps,dwc-ahci";
reg = <0 0xe0300000 0 0xf0000>;
interrupts = <0 355 4>;
clocks = <&sataclk_333mhz>;
iommus = <&sata0_smmu 0x0 0x1f>;
dma-coherent;
};
/* This is for Rev B only */
sata1: sata@e0d00000 {
status = "disabled";
compatible = "snps,dwc-ahci";
reg = <0 0xe0d00000 0 0xf0000>;
interrupts = <0 354 4>;
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.