arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
Extension
.dtsi
Size
24801 bytes
Lines
1131
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/amlogic,c3-reset.h>
#include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
#include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
#include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
#include <dt-bindings/power/amlogic,c3-pwrc.h>
#include <dt-bindings/gpio/amlogic-c3-gpio.h>

/ {
	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2>;
		};

		l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x7d000>; /* L2. 512 KB */
			cache-line-size = <64>;
			cache-sets = <512>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

Annotation

Implementation Notes