arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi- Extension
.dtsi- Size
- 5404 bytes
- Lines
- 223
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/irq.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/gpio/gpio.hdt-bindings/pinctrl/amlogic,pinctrl.hdt-bindings/power/amlogic,s6-pwrc.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
#include <dt-bindings/power/amlogic,s6-pwrc.h>
/ {
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0x0 0x200>;
enable-method = "psci";
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0x0 0x300>;
enable-method = "psci";
};
};
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
pwrc: power-controller {
compatible = "amlogic,s6-pwrc";
#power-domain-cells = <1>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/gpio/gpio.h`, `dt-bindings/pinctrl/amlogic,pinctrl.h`, `dt-bindings/power/amlogic,s6-pwrc.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.