arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
Extension
.dtsi
Size
17057 bytes
Lines
767
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/amlogic,t7-pwrc.h>
#include "amlogic-t7-reset.h"
#include <dt-bindings/clock/amlogic,t7-scmi.h>
#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu100>;
				};
				core1 {
					cpu = <&cpu101>;
				};
				core2 {
					cpu = <&cpu102>;
				};
				core3 {
					cpu = <&cpu103>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu100: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "psci";
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2_cache_l>;
		};

		cpu101: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";

Annotation

Implementation Notes