arch/arm64/boot/dts/amlogic/meson-a1.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/amlogic/meson-a1.dtsi- Extension
.dtsi- Size
- 17032 bytes
- Lines
- 766
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/amlogic,a1-pll-clkc.hdt-bindings/clock/amlogic,a1-peripherals-clkc.hdt-bindings/gpio/meson-a1-gpio.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/interrupt-controller/irq.hdt-bindings/power/meson-a1-power.hdt-bindings/reset/amlogic,meson-a1-reset.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
#include <dt-bindings/gpio/meson-a1-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/meson-a1-power.h>
#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
/ {
compatible = "amlogic,a1";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
d-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-sets = <32>;
i-cache-line-size = <32>;
i-cache-size = <0x8000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>; /* L2. 512 KB */
cache-line-size = <64>;
cache-sets = <512>;
};
};
efuse: efuse {
compatible = "amlogic,meson-gxbb-efuse";
clocks = <&clkc_periphs CLKID_OTP>;
#address-cells = <1>;
#size-cells = <1>;
secure-monitor = <&sm>;
Annotation
- Immediate include surface: `dt-bindings/clock/amlogic,a1-pll-clkc.h`, `dt-bindings/clock/amlogic,a1-peripherals-clkc.h`, `dt-bindings/gpio/meson-a1-gpio.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/power/meson-a1-power.h`, `dt-bindings/reset/amlogic,meson-a1-reset.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.