arch/arm64/boot/dts/apple/spi1-nvram.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/apple/spi1-nvram.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/apple/spi1-nvram.dtsi- Extension
.dtsi- Size
- 653 bytes
- Lines
- 38
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Devicetree include for common spi-nor nvram flash.
//
// Apple uses a consistent configuration for the nvram on all known M1* and
// M2* devices.
//
// Copyright The Asahi Linux Contributors
/ {
aliases {
nvram = &nvram;
};
};
&spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
nvram: partition@700000 {
label = "nvram";
/* To be filled by the loader */
reg = <0x0 0x0>;
status = "disabled";
};
};
};
};
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.