arch/arm64/boot/dts/apple/t7001.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/apple/t7001.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/apple/t7001.dtsi
Extension
.dtsi
Size
6981 bytes
Lines
281
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Apple T7001 "A8X" SoC
 *
 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org>
 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>

/ {
	interrupt-parent = <&aic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &serial0;
	};

	clkref: clock-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "clkref";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "apple,typhoon";
			reg = <0x0 0x0>;
			cpu-release-addr = <0 0>; /* To be filled in by loader */
			performance-domains = <&cpufreq>;
			operating-points-v2 = <&typhoon_opp>;
			enable-method = "spin-table";
			device_type = "cpu";
			next-level-cache = <&l2_cache>;
			i-cache-size = <0x10000>;
			d-cache-size = <0x10000>;
		};

		cpu1: cpu@1 {
			compatible = "apple,typhoon";
			reg = <0x0 0x1>;
			cpu-release-addr = <0 0>; /* To be filled in by loader */
			performance-domains = <&cpufreq>;
			operating-points-v2 = <&typhoon_opp>;
			enable-method = "spin-table";
			device_type = "cpu";
			next-level-cache = <&l2_cache>;
			i-cache-size = <0x10000>;
			d-cache-size = <0x10000>;
		};

		cpu2: cpu@2 {
			compatible = "apple,typhoon";
			reg = <0x0 0x2>;
			cpu-release-addr = <0 0>; /* To be filled by loader */
			performance-domains = <&cpufreq>;
			operating-points-v2 = <&typhoon_opp>;
			enable-method = "spin-table";
			device_type = "cpu";
			next-level-cache = <&l2_cache>;
			i-cache-size = <0x10000>;
			d-cache-size = <0x10000>;

Annotation

Implementation Notes