arch/arm64/boot/dts/apple/t8015-pmgr.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/apple/t8015-pmgr.dtsi- Extension
.dtsi- Size
- 24115 bytes
- Lines
- 933
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* PMGR Power domains for the Apple T8015 "A11" SoC
*
* Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com>
*/
&pmgr {
ps_cpu0: power-controller@80000 {
compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x80000 4>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "cpu0";
apple,always-on; /* Core device */
};
ps_cpu1: power-controller@80008 {
compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x80008 4>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "cpu1";
apple,always-on; /* Core device */
};
ps_cpu2: power-controller@80010 {
compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x80010 4>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "cpu2";
apple,always-on; /* Core device */
};
ps_cpu3: power-controller@80018 {
compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x80018 4>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "cpu3";
apple,always-on; /* Core device */
};
ps_cpu4: power-controller@80020 {
compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x80020 4>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "cpu4";
apple,always-on; /* Core device */
};
ps_cpu5: power-controller@80028 {
compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x80028 4>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "cpu5";
apple,always-on; /* Core device */
};
ps_cpm: power-controller@80040 {
compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x80040 4>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "cpm";
apple,always-on; /* Core device */
};
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.