arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/arm/corstone1000-a320.dtsi- Extension
.dtsi- Size
- 1884 bytes
- Lines
- 92
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hcorstone1000.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (c) 2026, Arm Limited. All rights reserved.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "corstone1000.dtsi"
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a320";
reg = <0 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a320";
reg = <0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a320";
reg = <0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a320";
reg = <0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
sram: sram@2400000 {
compatible = "mmio-sram";
reg = <0x02400000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
gic: interrupt-controller@1c000000 {
compatible = "arm,gic-v3";
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `corstone1000.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.