arch/arm64/boot/dts/arm/corstone1000.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/arm/corstone1000.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/arm/corstone1000.dtsi
Extension
.dtsi
Size
3525 bytes
Lines
149
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (c) 2022, Arm Limited. All rights reserved.
 * Copyright (c) 2022, Linaro Limited. All rights reserved.
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@88200000 {
		device_type = "memory";
		reg = <0x88200000 0x77e00000>;
	};

	gic: interrupt-controller@1c000000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x1c010000 0x1000>,
		      <0x1c02f000 0x2000>,
		      <0x1c04f000 0x1000>,
		      <0x1c06f000 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
			      IRQ_TYPE_LEVEL_LOW)>;
	};

	L2_0: l2-cache0 {
		compatible = "cache";
		cache-unified;
		cache-level = <2>;
		cache-size = <0x80000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
	};

	refclk100mhz: clock-100000000 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "apb_pclk";
	};

	smbclk: clock-48000000 {
		/* Reference 24MHz clock x 2 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <48000000>;
		clock-output-names = "smclk";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

Annotation

Implementation Notes