arch/arm64/boot/dts/arm/foundation-v8.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/arm/foundation-v8.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/arm/foundation-v8.dtsi
Extension
.dtsi
Size
6712 bytes
Lines
239
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x80000000 0x00010000;

/ {
	model = "Foundation-v8A";
	compatible = "arm,foundation-aarch64", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
		};
		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			next-level-cache = <&L2_0>;
		};
		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x80000000>,

Annotation

Implementation Notes