arch/arm64/boot/dts/arm/juno-base.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/arm/juno-base.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/arm/juno-base.dtsi
Extension
.dtsi
Size
23858 bytes
Lines
996
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
#include "juno-clocks.dtsi"
#include "juno-motherboard.dtsi"

/ {
	/*
	 *  Devices shared by all Juno boards
	 */

	memtimer: timer@2a810000 {
		compatible = "arm,armv7-timer-mem";
		reg = <0x0 0x2a810000 0x0 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0x2a820000 0x20000>;
		status = "disabled";
		frame@2a830000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10000 0x10000>;
		};
	};

	mailbox: mhu@2b1f0000 {
		compatible = "arm,mhu", "arm,primecell";
		reg = <0x0 0x2b1f0000 0x0 0x1000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <1>;
		clocks = <&soc_refclk100mhz>;
		clock-names = "apb_pclk";
	};

	smmu_gpu: iommu@2b400000 {
		compatible = "arm,mmu-400", "arm,smmu-v1";
		reg = <0x0 0x2b400000 0x0 0x10000>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
		power-domains = <&scpi_devpd 1>;
		dma-coherent;
		status = "disabled";
	};

	smmu_pcie: iommu@2b500000 {
		compatible = "arm,mmu-401", "arm,smmu-v1";
		reg = <0x0 0x2b500000 0x0 0x10000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
		dma-coherent;
		status = "disabled";
	};

	smmu_etr: iommu@2b600000 {
		compatible = "arm,mmu-401", "arm,smmu-v1";
		reg = <0x0 0x2b600000 0x0 0x10000>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
		dma-coherent;
		power-domains = <&scpi_devpd 0>;
	};

	gic: interrupt-controller@2c010000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";

Annotation

Implementation Notes