arch/arm64/boot/dts/arm/morello-fvp.dts

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/arm/morello-fvp.dts

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/arm/morello-fvp.dts
Extension
.dts
Size
1809 bytes
Lines
78
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
 */

/dts-v1/;
#include "morello.dtsi"

/ {
	model = "Arm Morello Fixed Virtual Platform";
	compatible = "arm,morello-fvp", "arm,morello";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	bp_refclock24mhz: clock-24000000 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "bp:clock24mhz";
	};

	block_0: virtio-block@1c170000 {
		compatible = "virtio,mmio";
		reg = <0x0 0x1c170000 0x0 0x200>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	};

	net_0: virtio-net@1c180000 {
		compatible = "virtio,mmio";
		reg = <0x0 0x1c180000 0x0 0x200>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	};

	rng_0: virtio-rng@1c190000 {
		compatible = "virtio,mmio";
		reg = <0x0 0x1c190000 0x0 0x200>;
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	};

	p9_0: virtio-p9@1c1a0000 {
		compatible = "virtio,mmio";
		reg = <0x0 0x1c1a0000 0x0 0x200>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	};

	kmi_0: kmi@1c150000 {
		compatible = "arm,pl050", "arm,primecell";
		reg = <0x0 0x1c150000 0x0 0x1000>;
		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
		clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi_1: kmi@1c160000 {
		compatible = "arm,pl050", "arm,primecell";
		reg = <0x0 0x1c160000 0x0 0x1000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
		clock-names = "KMIREFCLK", "apb_pclk";
	};

	eth_0: ethernet@1d100000 {
		compatible = "smsc,lan91c111";
		reg = <0x0 0x1d100000 0x0 0x10000>;

Annotation

Implementation Notes