arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
Extension
.dts
Size
3334 bytes
Lines
153
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * LogicTile Express 20MG
 * V2F-1XV7
 *
 * Cortex-A53 (2 cores) Soft Macrocell Model
 *
 * HBI-0247C
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "arm/arm/vexpress-v2m-rs1.dtsi"

/ {
	model = "V2F-1XV7 Cortex-A53x2 SMM";
	arm,hbi = <0x247>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		stdout-path = "serial0:38400n8";
	};

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0 0>;
			next-level-cache = <&L2_0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0 1>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
	};

	reserved-memory {

Annotation

Implementation Notes