arch/arm64/boot/dts/arm/zena-css.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/arm/zena-css.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/arm/zena-css.dtsi
Extension
.dtsi
Size
17967 bytes
Lines
770
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
 * Copyright (c) 2025, Arm Limited. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	soc_clk24mhz: clock-24000000 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "refclk24mhz";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		/*
		 * The latency and residency numbers below are for illustrative
		 * purposes only and may vary on actual silicon. These values are
		 * considered just to demonstrate that the cpuidle governor logic
		 * works.
		 */
		idle-states {
			entry-method = "psci";

			cpu_sleep: cpu-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x10000>;
				entry-latency-us = <800>;
				exit-latency-us = <3200>;
				local-timer-stop;
				min-residency-us = <4200>;
			};

			cluster_sleep: cluster-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <1000>;
				exit-latency-us = <3200>;
				local-timer-stop;
				min-residency-us = <4500>;
			};
		};

		cpu-map {
			cluster0 {
				core0 { cpu = <&cpu0>; };
				core1 { cpu = <&cpu1>; };
				core2 { cpu = <&cpu2>; };
				core3 { cpu = <&cpu3>; };
			};

			cluster1 {
				core0 { cpu = <&cpu4>; };
				core1 { cpu = <&cpu5>; };
				core2 { cpu = <&cpu6>; };
				core3 { cpu = <&cpu7>; };
			};

			cluster2 {
				core0 { cpu = <&cpu8>; };
				core1 { cpu = <&cpu9>; };
				core2 { cpu = <&cpu10>; };

Annotation

Implementation Notes