arch/arm64/boot/dts/aspeed/aspeed-g7-soc0.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/aspeed/aspeed-g7-soc0.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/aspeed/aspeed-g7-soc0.dtsi- Extension
.dtsi- Size
- 6796 bytes
- Lines
- 231
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/aspeed,ast2700-scu.hdt-bindings/reset/aspeed,ast2700-scu.hdt-bindings/interrupt-controller/aspeed-scu-ic.haspeed-g7-soc0-pinctrl.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AST27xx SoC Family Main Domain peripherals
*
* Copyright (C) 2026 ASPEED Technology Inc.
*/
#include <dt-bindings/clock/aspeed,ast2700-scu.h>
#include <dt-bindings/reset/aspeed,ast2700-scu.h>
#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
&soc0 {
sram0: sram@10000000 {
compatible = "mmio-sram";
reg = <0x0 0x10000000 0x0 0x20000>;
ranges = <0x0 0x0 0x10000000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
soc0-sram@0 {
reg = <0x0 0x20000>;
export;
};
};
vhuba1: usb-vhub@12011000 {
compatible = "aspeed,ast2700-usb-vhub";
reg = <0x0 0x12011000 0x0 0x820>;
interrupts-extended = <&intc0 32>;
clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>;
resets = <&syscon0 SCU0_RESET_PORTA_VHUB>;
aspeed,vhub-downstream-ports = <7>;
aspeed,vhub-generic-endpoints = <21>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2axhpd1_default>;
status = "disabled";
};
vhubb1: usb-vhub@12021000 {
compatible = "aspeed,ast2700-usb-vhub";
reg = <0x0 0x12021000 0x0 0x820>;
interrupts-extended = <&intc0 36>;
clocks = <&syscon0 SCU0_CLK_GATE_PORTBUSB2CLK>;
resets = <&syscon0 SCU0_RESET_PORTB_VHUB>;
aspeed,vhub-downstream-ports = <7>;
aspeed,vhub-generic-endpoints = <21>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2bxhpd1_default>;
status = "disabled";
};
uhci0: usb@12040000 {
compatible = "aspeed,ast2700-uhci", "generic-uhci";
reg = <0x0 0x12040000 0x0 0x100>;
interrupts-extended = <&intc0 10>;
#ports = <2>;
clocks = <&syscon0 SCU0_CLK_GATE_UHCICLK>;
resets = <&syscon0 SCU0_RESET_UHCI>;
status = "disabled";
};
vhuba0: usb-vhub@12060000 {
compatible = "aspeed,ast2700-usb-vhub";
reg = <0x0 0x12060000 0x0 0x820>;
interrupts-extended = <&intc0 33>;
clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>;
resets = <&syscon0 SCU0_RESET_PORTA_VHUB_EHCI>;
aspeed,vhub-downstream-ports = <7>;
aspeed,vhub-generic-endpoints = <21>;
pinctrl-names = "default";
Annotation
- Immediate include surface: `dt-bindings/clock/aspeed,ast2700-scu.h`, `dt-bindings/reset/aspeed,ast2700-scu.h`, `dt-bindings/interrupt-controller/aspeed-scu-ic.h`, `aspeed-g7-soc0-pinctrl.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.